Revision History - 3.1 English

UltraScale Architecture Soft Error Mitigation Controller LogiCORE IP Product Guide (PG187)

Document ID
PG187
Release Date
2024-06-05
Version
3.1 English

The following table shows the revision history for this document.

Section Revision Summary
06/05/2024 Version 3.1
Product Specification Added support for device XCAU7P.
11/8/2023 Version 3.1
Product Specification Updated Mode Features table to include XCKU19P for AMD UltraScale+™
Monitor Interface Signaling and Protocol Fixed Monitor Interface Receive Protocol clocking diagram
Designing with the Core Fixed Timing Diagram for Switching Behaviour for Auxiliary Interface
05/17/2023 Version 3.1
Overview Updated section, Encryption and Authentication Support for RSA authentication and AES encryption with key rolling.
11/05/2022 Version 3.1
Product Specification Updated Table 2-2.
10/27/2021 Version 3.1
Product Specification Added XCZU1, XCAU20P, XCAU15P, and XCAU10P in Table 2-2, Table 2-6, Table 2-8
Designing with the Core
  • Added LUTROM functions in Configuration Memory Masking.
  • Updated Table 3-7
08/06/2021 Version 3.1
Product Specification and Designing with the Core Added XCUX35 and XCAU25P in Table 2-2, Table 2-6, Table 2-8
02/04/2021 Version 3.1
Product Specification, Designing with the Core and Example Design Updated Table 2-2, Table 2-6, Table 2-8, Table 3-7, and Table 5-1.
Product Specification and Designing with the Core Added XCVU45P, XCVU47P, XCZU46DR, XCZU47DR, XCZU48DR, and XCZU49DR in Table 2-2, Table 2-6, Table 2-8, and Table 3-7.
Example Design Added VU45P and VU47P in Table 5-1.
05/22/2019 Version 3.1
Product Specification Added XCVU27P and XCVU29P in Table 2-2, Table 2-6, and Table 2-8.
Designing with the Core
  • Added detection report description in Error Detection Report – Mitigation Modes (Correction Enabled), Error Detection Report – Detect Only, and Error Detection Report – Diagnostic Scan.
  • Added UART note in UART Interface Commands.
  • Added XCVU27P and XCVU29P in Table 3-7.
Example Design Added VU27P/VU29P in Table 5-1.
Fetch Interface Signaling and Protocol Removed headings
11/14/2018 Version 3.1
Overview Added Partial Reconfiguration Support and space radiation description in Unsupported Features section
04/04/2018 Version 3.1
Overview Updated Unsupported Features section
Product Specification Updated Solution Reliability section
Designing with the Core Updated System Clock Interface section
Fetch Interface Signaling and Protocol Updated content and added note for boot state
12/20/2017 Version 3.1
Overview
  • Updated Overview description.
  • Added Key Considerations for SEM IP Adoption
  • Updated Encryption and Authentication Support section.
Product Specification
  • Added footnote to XCVU9P in Maximum Start-up Latency at ICAP FMax for UltraScale+ Devices and Maximum IP Error Detection Times at ICAP FMax for UltraScale+ Devices tables.
  • Added footnote to UltraScale+ Monolithic and UltraScale+ SSI in Error Correction Latency section.
  • Added footnote to UltraScale+ Monolithic and UltraScale+ SSI in Error Classification Latency section.
  • Added footnote to UltraScale+ VU3P and UltraScale+ SSI VU9P in Error Injection Latency section.
  • Updated Status Interface Heartbeat Switching Characteristics for KU040 figure.
  • Added description to Monitor Interface
Designing with the Core Updated SC code in Initialization Report
10/04/2017 Version 3.1
Introduction Updated IP Facts.
Overview Removed UltraScale+ Device Support
Product Specification
  • Added XCVU31P to XCVU37P and XCZU21DR to XCZU29DR device information
  • Added UltraScale+ SSI description to Error Classification Latency, No Throttling on Monitor Interface table.
  • Added UltraScale+ SSI VU3P description to Error Injection Latency When Using Linear Frame Addressing, No Throttling on Monitor Interface table.
  • Added VU9P description to Device Utilization – Multi-SLR UltraScale and UltraScale+ Devices (SSI) table.
  • Added description to status_essential in Status Interface Signals table.
  • Added description to the status_essential Tip in Classification (Mitigation Modes Only) section.
  • Added description in Fetch Interface section.
Designing with the Core
  • Updated UltraScale+ description to External Storage Requirements table.
  • Added description in Required Constraints

Example Design

Added SSI device descriptions in External Memory Programming File section.

Status Report Added SSI device description
04/05/2017 Version 3.1
Introduction Added new supported devices in IP Facts note.
Overview
  • Updated UltraScale+ Device Support sections.
  • Added golden/fallback description in Unsupported Features section.
Product Specification
  • Added devices in Maximum Number of Configuration Frames to Error Correction Latency, No Throttling on Monitor Interface tables.
  • Updated description in Resource Utilization section.
  • Updated description in Port Descriptions section.
  • Added description to FRAME_ECC and Status Interface sections.
  • Updated description in General Design Guidelines section.
  • Updated description in Systems section.
  • Added note in Structural Options section.
Designing with the Core
  • Added description to FRAME_ECC and Status Interface sections
  • Added Zynq UltraScale+ MPSoC Considerations section.
  • Added description to Command Interface section.
  • Added note in Configuration Primitive Included in Core section.
  • Added UltraScale+ in External Storage Requirements table.
Design Flow Steps
  • Updated description in Customizing and Generating the Core section.
  • Added description in Placement Constraints and Pin Constraints sections.
  • Added description in Constraints for UltraScale/UltraScale+ SSI Devices sections.
  • Added description in Functions section.
  • Updated description in Port Descriptions section.
  • Updated code in Creating the External Memory Programming File section.
Using an Evaluation Board to Demonstrate SEM Controller Behavior Added Zynq UltraScale+ and Virtex UltraScale+
Error Injection Guidance Added UltraScale+ description
IP Design Checklist Added description
Example Design Updated code.
10/05/2016 Version 3.1
Introduction Added new supported devices in IP Facts note.
Overview
  • Updated UltraScale+ Device Support sections.
  • Added golden/fallback description in the Unsupported Features section.
Product Specification
  • Added devices in Maximum Number of Configuration Frames to Error Correction Latency, No Throttling on Monitor Interface tables.
  • Updated UltraScale+ in Maximum Estimated FIT Rate table.
  • Added UltraScale+ devices in Maximum Start-up Latency at ICAP FMax table.
  • Added UltraScale+ devices in Maximum IP Error Detection Times at ICAP FMax table.
  • Added UltraScale+ devices in Error Correction Latency, No Throttling on Monitor Interface, Error Classification Latency, No Throttling on Monitor Interface, and Error Injection Latency When Using Linear Frame Addressing, No Throttling on Monitor Interface tables.
  • Updated SEM Controller Ports figure.
Designing with the Core
  • Added description on UltraScale+ SSI devices
  • Changed monitor_rx/tx to uart_rx/tx.
  • Added description in Initialization section
Example UART Logs Added new appendix.
04/06/2016 Version 3.1
Product Specification
  • Added support for UltraScale+ families.
  • Added Detect and Testing and Detect only modes in document.
  • Updated Fig. 2-1: SEM Controller Ports.
Designing with the Core
  • Updated Table 3-2: Command Format and Usage.
  • Updated Error Detection Report – Mitigation Modes (Correction Enabled) section.
  • Updated Error Detection Report – Detect Only section.
  • Updated Error Detection Report – Diagnostic Scan section.
  • Updated Table 3-5: UART Commands and Usage.
Design Flow Steps Updated the chapter
Example Design Updated Creating the External Memory Programming File section.
Verification, Compliance, and Interoperability Updated Verification section
Upgrading Added UltraScale+ description
Using an Evaluation Board to Demonstrate SEM Controller Behavior Added SPI Bus Timing
IP Design Checklist Added Post-Synthesis DCP
09/30/2015 Version 3.0
Introduction
  • Added Detect only and Diagnostic Scan states throughout document.
  • Updated IP Facts section.
  • Added description to Features Summary section.
  • Added detect feature description in Features section.
Product Specification
  • Added Table 2-2: Maximum Number of Configuration Frames.
  • Updated Table 2-5: Maximum Start-up Latency at ICAP FMax.
  • Updated Table 2-6: Maximum IP Error Detection Times at ICAP FMax.
  • Updated Table 2-9: Error Injection Latency When Using Physical Frame Addressing, No Throttling on Monitor Interface.
  • Added description in Sources of Additional Latency section.
  • Updated Resource Utilization section.
  • Updated Fig. 2-1: SEM Controller Ports.
  • Updated description in Status Interface section.
Designing with the Core
  • Added Integrate and Validate Early description in General Design Guidelines section.
  • Updated ICAP Arbitration Interface section.
  • Updated Figs. 3-4 to 3-6.
  • Added Directed State Change for Detect only and Diagnostic states.
  • Updated description and figure in Heartbeat section.
  • Updated UART Interface section.
  • Updated Systems section.
Design Flow Steps
  • Updated GUIs in Figs. 4-1 to 4-3.
  • Updated User Parameter section.
  • Updated Functions section.
  • Added descriptions in Controller Constraints, Example Design Constraints, and Constraints for SSI Devices sections.
  • Added Integration and Validation section in Design Flow Steps chapter.
Example Design Updated Table 5-1: Device Number SLR.
Upgrading, Error Injection Guidance, IP Design Checklist Added appendices.
Debugging Added Additional Error Injection Options, Device Dependency and Other Incompatibilities.
04/01/2015 Version 2.0
Initial release. N/A