Port Descriptions - 3.1 English

UltraScale Architecture Soft Error Mitigation Controller LogiCORE IP Product Guide (PG187)

Document ID
PG187
Release Date
2024-06-05
Version
3.1 English

The following figure shows the example design ports for all devices. The ports are clustered into three groups. The groups shaded in gray only exist when the error classification feature is enabled.

Figure 1. Example Design Ports

In an SSI device, each SLR is numbered. There are two numbering methods: hardware SLR numbering and software SLR numbering.

A hardware SLR number represents the configuration order of the SLR in the device. The Master SLR, which is always present, is hardware SLR 0. The hardware SLR numbers of additional Slave SLRs are approximately assigned radially outward from the Master SLR.

For UltraScale devices, a controller instance located in an SLR determines the hardware SLR number at runtime by reading the IDCODE register through the ICAP on the SLR. In all command and status exchanges with controllers implemented in an SSI device, hardware SLR numbering is used.

A software SLR number represents the bottom-to-top physical order of the SLR in the device. The Master SLR, which is always present, has a software SLR number that varies by device. The software SLR numbers are prominently visible in the device view presented by the AMD development software.

The following table details the mapping between hardware SLR numbers and software SLR numbers.

Table 1. Device Number SLR
Device Software SLR Number Hardware SLR Number SLR Type
KU115 1 1 Slave
0 0 Master
VU125 1 1 Slave
0 0 Master
VU190 2 2 Slave
1 0 Master
0 1 Slave
VU440 2 2 Slave
1 0 Master
0 1 Slave
VU5P/VU7P/VU35P/VU45P 1 1 Slave
0 0 Master
VU9P 2 2 Slave
1 0 Master
0 1 Slave
VU11P/VU37P/VU47P 2 2 Slave
1 1 Slave
0 0 Master
VU13P 3 3 Slave
2 2 Slave
1 0 Master
0 1 Slave
VU27P/VU29P 3 3 Slave
2 2 Slave
1 0 Master
0 1 Slave
U55N 1 1 Slave
0 0 Master
U55C 2 2 Slave
1 1 Slave
0 0 Master
XCVU57P 2 2 Slave
1 1 Slave
0 0 Master
XCVU19P 3 3 Slave
2 2 Slave
1 0 Master
0 1 Slave
XCVU15P 3 3 Slave
2 2 Slave
1 0 Master
0 1 Slave
XCVU23P 0 0 Master
XCK26 1 1 Slave
0 0 Master
Note: Understanding and translating the SLR numbering methods is not necessary for successful implementation of controllers in an SSI device. However, this information might be useful with error injection if it is desired to direct an injected error to a specific SLR.

The example design ports for UltraScale SSI devices are the same as monolithic devices because the delivered UART and SPI flash master helper blocks combine all the Fetch and Monitor Interfaces of each controller (per SLR) to provide a single interface to manage and interact with IPs. However, if the ports on the support_wrapper hierarchy are inspected, you will find that some interface ports (for example, Status Interface) become buses, where the bus width is determined by the number of SLRs in the SSI devices.

The system-level design example does not have a reset port. The controller automatically initializes itself. The controller then initializes the helper blocks, as required.

The system-level design example is a fully synchronous design using clk as the single clock. All state elements are synchronous to the rising edge of this clock. As a result, the interfaces are generally synchronous to the rising edge of this clock.

All interfaces available in the system-level design example including their system requirements has been discussed in Product Specification and Designing with the Core in detail. The following links are given as a convenience:

System Clock Interface
Port Description (System Clock Interface) and Usage (System Clock Interface).
Status Interface
Port Description (Status Interface) and Usage (Status Interface).
Command Interface
Port Description (Command Interface) and Usage (Command Interface).
UART Interface
Port Description (UART Interface) and Usage (UART Interface).
SPI Interface
Port Description (SPI Interface) and Usage (SPI Interface).