References - 3.1 English - PG187

These documents provide supplemental material useful with this guide:

1. Device Reliability Report (UG116)
2. UltraScale Architecture Configuration User Guide (UG570)
3. Zynq UltraScale+ Device Technical Reference Manual (UG1085)
4. Integrating LogiCORE SEM IP in Zynq UltraScale+ Devices (XAPP1298)
5. Integrating LogiCORE SEM IP with AXI in Zynq UltraScale+ Devices (XAPP1303)
6. Demonstration of Soft Error Mitigation IP and Partial Reconfiguration Capability on Monolithic Devices (XAPP1261)
7. Zynq UltraScale+ MPSoC: Software Developers Guide (UG1137)
8. BSP and Libraries Document Collection (UG643)
9. Vivado Design Suite User Guide: Logic Simulation (UG900)
10. Vivado Design Suite User Guide: Implementation (UG904)
11. Vivado Design Suite User Guide: Designing with IP (UG896)
12. Vivado Design Suite User Guide: Programming and Debugging (UG908)
13. Vivado Design Suite User Guide: Getting Started (UG910)
14. Vivado Design Suite User Guide: Release Notes, Installation, and Licensing (UG973)
15. Vivado Design Suite User Guide: Designing IP Subsystems using IP Integrator (UG994)
16. Vivado Design Suite User Guide: Getting Started (UG910)