Constraints for UltraScale+ SSI Devices - 3.1 English

UltraScale Architecture Soft Error Mitigation Controller LogiCORE IP Product Guide (PG187)

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3.1 English

In the system-level design example, only one controller instance is generated but two to four FRAME_ECC instances are generated depending on the device. The FRAME_ECC instances are named to include an identification number ranging from 0 to 3. The controller instance numbering matches the hardware SLR number.

For the tool to place the ICAP and FRAME_ECC primitives correctly, the following constraints need to be applied (this is an example of two SLR devices):

# Force FRAME_ECC to the site in this SLR.
set_property LOC CONFIG_SITE_X0Y1 [get_cells example_support_wrapper/example_support/example_cfg/slr1_cfg_frame_ecce4]
set_property LOC CONFIG_SITE_X0Y0 [get_cells example_support_wrapper/example_support/example_cfg/slr0_cfg_frame_ecce4]
# Force ICAP to the site in this SLR.
set_property LOC CONFIG_SITE_X0Y0 [get_cells example_support_wrapper/example_support/example_cfg/cfg_icape3]

An area constraint is applied to the controller to place it in the Master SLR to keep the controller located near the associated ICAP.

To ease timing closure, the shared blocks such as UART and SPI flash master helper blocks might also have area constraints to locate them in the Master SLR, which is centrally located in the device.

When selecting I/O pins for the UART or SPI flash interface, AMD recommends that these I/O pins are placed in an I/O bank within the Master SLR and closest to the controller.