Required Constraints - 3.1 English

UltraScale Architecture Soft Error Mitigation Controller LogiCORE IP Product Guide (PG187)

Document ID
PG187
Release Date
2024-06-05
Version
3.1 English

The SEM controller and the system-level design example require the specification of physical implementation constraints to yield a functional result that meets performance requirements. These constraints are provided with the system-level design example in an XDC file or files.

For the AMD UltraScale+™ example design, two XDC constraints are delivered; one containing timing (*_synth.xdc ) and one containing placement constraints (*_impl.xdc ). For the UltraScale example design, a single XDC constraint is delivered containing both the timing and placement constraints. Regardless the number of XDC files delivered, the type of constraints in the XDC file or files are the same.

To achieve consistent implementation results, the XDC provided with the solution must be used. For additional details on the definition and use of a XDC or specific constraints, see the Constraints Guide available through the documentation page for the Vivado Design Suite.

Constraints might require modification to integrate the solution into a larger project, or as a result of changes made to the system-level design example. Modifications should only be made with a thorough understanding of the effect of each constraint. Additionally, support is not provided for designs that deviate from the provided constraints.