SPI Interface - 3.1 English - PG187

UltraScale Architecture Soft Error Mitigation Controller LogiCORE IP Product Guide (PG187)
Document ID
PG187
Release Date
2025-01-15
Version
3.1 English

The SPI Interface consists of four signals implementing an SPI bus protocol compatible, full duplex serial port. This interface is only present when the Error Classification feature is enabled. The implementation of this function requires external storage. The system-level design example provides a fixed-function SPI bus master in the SPI flash master helper block to fetch data from a single external SPI flash device. The following figure provides the SPI flash density requirement for each supported FPGA.

Table 1. External Storage Requirements
Device Storage Requirements for Error Classification (Mb)
UltraScale XCKU035 128
XCKU040 128
XCKU060 256
XCKU085 512
XCKU115 512
XCVU065 256
XCVU080 256
XCVU095 256
XCVU125 512
XCVU160 1,024
XCVU190 1,024
XCVU440 1 1,024
UltraScale+ XCKU3P 128
XCKU5P 128
XCKU9P 256
XCKU11P 256
XCKU13P 256
XCKU15P 256
XCVU3P 256
XCVU5P 512
XCVU7P 512
XCVU9P 512
XCVU11P 1024
XCVU13P 1024
XCVU27P 1024
XCVU29P 1024
XCVU31P 256
XCVU33P 256
XCVU35P 512
XCVU37P 1024
XCVU45P 512
XCVU47P 1024
XCZU1 32
XCZU2 32
XCZU3 32
XCZU4 64
XCZU5 64
XCZU6 256
XCZU7 256
XCZU9 256
XCZU11 256
XCZU15 256
XCZU17 256
XCZU19 256
UltraScale+ (Continued) XCZU21DR 256
XCZU25DR 256
XCZU27DR 256
XCZU28DR 256
XCZU29DR 256
XCZU46DR 256
XCZU47DR 256
XCZU48DR 256
XCZU49DR 256
U55N 512
U55C 1024
XCVU57P 1024
XCVU19P 1024
XCVU15P 1024
XCVU23P 256
XCK26 64
XCUX35 256
XCAU25P 128
XCAU20P 128
XCAU15P 128
XCAU7P 32
  1. XCVU440 requires the use of SPI flash memory devices (for example, the MT25Q devices) that can read seamlessly with a single command across any die boundaries.

The SPI flash master helper block uses the fast read command (0x0B ) and can be configured to support one of several different families of SPI flash. The family supported by default depends on the external storage requirements shown in the previous table. In the SPI flash master helper block system-level example design module, there are three parameters that control the command sequence sent to the SPI flash device.

B_ISSUE_WREN
Indicates if a write enable command (0x06 ) must be issued prior to any other commands that modify the device behavior. Must be set to 1 for N25Q and MT25Q devices, but generally set to 0 for other devices.
B_ISSUE_WVCR
Indicates if a write volatile configuration register command (0x81 ) must be issued to explicitly set the fast read dummy cycle count to eight cycles. The state machine in the SPI flash master helper block is byte-oriented and expects the fast read dummy cycle count to be eight. The volatile configuration register data is overwritten (0x8B ). Must be set to 1 for N25Q and MT25Q devices, but generally set to 0 for other devices.
B_ISSUE_EN4B
Indicates if an enable 4-byte addressing command (0xB7 ) must be issued to explicitly enter the 4-byte addressing mode. Must be set to 1 for devices > 128 Mbits.

For storage requirements £ 128 Mbits, the SPI flash master helper block supports M25P devices by default (B_ISSUE_WREN = 0, B_ISSUE_WVCR = 0, B_ISSUE_EN4B = 0). These devices are not capable of 4-byte addressing mode.

For storage requirements > 128 Mbits, the SPI flash master helper block supports higher-density N25Q and MT25Q devices by default (B_ISSUE_WREN = 1, B_ISSUE_WVCR = 1, B_ISSUE_EN4B = 1). These devices are capable of 4-byte addressing mode.

Other supported devices include lower-density N25Q devices for storage requirements £ 128 Mbits (B_ISSUE_WREN = 1, B_ISSUE_WVCR = 1, B_ISSUE_EN4B = 0) and higher-density MX25 devices for storage requirements > 128 Mbits (B_ISSUE_WREN = 0, B_ISSUE_WVCR = 0, B_ISSUE_EN4B = 1).

Note: The SPI flash master helper block implementation supports only one SPI flash read command (fast read) in SPI Mode 0 (CPOL = 0, CPHA = 0) to a single SPI flash device.

The following figure shows the connectivity between an FPGA and SPI flash device. Note the presence of level translators (marked “LT”). These are required because commonly available SPI flash devices use 3.3V I/O, which might not be available depending on the selected FPGA or I/O bank voltage.

Figure 1. SPI Flash Device Connection, Including Level Translators

The level translators must exhibit low propagation delay to maximize the SPI bus performance. The SPI bus performance can potentially affect the maximum frequency of operation of the entire system-level design example.

Note: Information on the switching behavior, system-level requirements, and example SPI bus timing budgets are in SPI Bus Timing Budget.

When using the error classification feature, the controller requires access to externally stored data. This data is created by write_bitstream at the same time the programming file for the FPGA is created.

Any time the FPGA design is changed and a new programming file is created, the additional data files used by the controller must also be updated. When the hardware design is updated with the new programming file, the externally stored data must also be updated.

Important: Failure to maintain data consistency can result in incorrect classification values being reported and leading to wrong mitigation actions being taken. AMD recommends use of an update methodology which ensures that the programming file and the additional data files are always synchronized.