Zynq UltraScale+ MPSoC Considerations - 3.1 English

UltraScale Architecture Soft Error Mitigation Controller LogiCORE IP Product Guide (PG187)

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3.1 English

Implementations that use the AMD Zynq™ UltraScale+™ MPSoCs must provide the SEM Controller access to the ICAP interface. This is performed by clearing the PCAP PR bit in the PS Configuration Security Unit (CSU) pcap_ctrl register.

During boot of the Zynq UltraScale+ MPSoC Processing System (PS), access to the configuration logic in the device is given to the PS through the Processor Configuration Access Port (PCAP). This provides a path for the PS bootloader to download a bitstream to the Zynq UltraScale+ MPSoC Programmable Logic (PL). When the PS bootloader is completed, the PS and PCAP remain in control of the configuration logic to support partial reconfiguration of the PL by the PS.

However, while the PS and PCAP are in control of the configuration logic, the PL and ICAP are locked out of the configuration logic. For the SEM controller to function, configuration logic access must be transferred to the ICAP. This is accomplished by clearing the pcap_pr (Bit[0]) in the PS CSU pcap_ctrl register (pcap_ctrl , address 0xFFCA3008 ). To confirm that the SEM controller has access to the configuration logic, ICAP_AVAIL can be monitored. If ICAP_AVAIL = 0, a higher priority master such as MCAP, PCAP, or JTAG has control of the configuration logic. If ICAP_AVAIL = 1, the SEM controller has access to the configuration.

For more information regarding PCAP, see the Zynq UltraScale+ Device Technical Reference Manual (UG1085).

When software running on the PS has completed all necessary PCAP activity, it clears PCAP_PR and sets the GPIO connected to the controller icap_grant input, allowing the controller to proceed with initialization. The signal applied to the icap_grant input must be properly synchronized to the icap_clk signal.

Although the software implementation of this behavior is outside the scope of this document, there are two application notes that can provide you with guidance on how to integrate the SEM controller with a PS. See Integrating LogiCORE SEM IP in Zynq UltraScale+ Devices (XAPP1298) and XAPP1303.

For detailed information about software development for Baremetal and Linux environments, see the Zynq UltraScale+ MPSoC: Software Developers Guide (UG1137) and BSP and Libraries Document Collection (UG643).