Configuration Register Reads (Peek Command) - Configuration Register Reads (Peek Command) - 3.1 English

Configuration Register Reads (Peek Command) - Configuration Register Reads (Peek Command) - 3.1 English - PG187

UltraScale Architecture Soft Error Mitigation Controller LogiCORE IP Product Guide (PG187)

Document ID

PG187

Release Date

2025-12-19

Version

3.1 English

The Configuration Register Read command reads certain configuration registers and reports its content. The format of the command is:

P {2-digit hex value}

The following table lists all the registers from which the SEM controller supports reads.

Table 1. Configuration Registers Readable Through Peek Command
Name	Address
CRC	00000
FAR	00001
CMD	00100
CTL0	00101
MASK	00110
STAT	00111
COR0	01001
IDCODE	01100
AXSS	01101
COR1	01110
WBSTAR	10000
TIMER	10001
BOOTSTS	10110

After execution of the Peek command, the controller returns data in the hexadecimal format as shown:

I> P 00
20BD8EDE
I>

UltraScale and UltraScale+ devices share the same format for the command and the returned data.

For more information on this register, see the UltraScale Architecture Configuration User Guide (UG570). For Spartan UltraScale+ FPGA, see the Spartan UltraScale+ FPGAs Configuration User Guide (UG860).