The controller classifies errors in the
Classification state. The controller always passes through the Classification state, even if
error classification is disabled. During the Classification state, status_classification is asserted High.
All errors signaled as uncorrectable during the
Correction state are signaled as essential. The only reason an error can be uncorrectable is
because it cannot be located. In this circumstance, the controller cannot look up the error to
determine whether it is essential. The controller asserts status_essential, generates a classification report on the Monitor Interface, and
transitions to the Idle state. After an uncorrectable error is encountered, the controller
does not continue looking for errors. Now, the FPGA must be reconfigured.
status_essential should be sampled at the falling edge of status_classification. This signal is sticky and does not update until the
controller corrects and classifies the next error. The treatment of errors signaled as correctable during the Correction state depends on the controller option setting. If error classification is disabled, all correctable errors are unconditionally signaled as essential. If error classification is enabled, the controller generates an essential bits data request on the Fetch Interface.
In the system-level design example, the SPI flash
master helper block translates this essential bits data request into a read of the external
memory. The returned data is provided to the controller by the SPI flash master helper block.
With this data, the controller determines whether it is essential. In all cases, the
controller generates a classification report on the Monitor Interface, changes status_essential as appropriate, and transitions to the Observation
state to resume looking for errors.