Initialization - 3.1 English

UltraScale Architecture Soft Error Mitigation Controller LogiCORE IP Product Guide (PG187)

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3.1 English

The controller is held inactive by the FPGA global set/reset signal. At the completion of configuration, the FPGA configuration system deasserts the global set/reset signal and the controller boots. The controller maintains all seven state bits on the Status Interface deasserted through the boot process.

The controller polls its cap_gnt and cap_rel input during boot to determine if it has been granted permission to enter the Initialization state and begin using ICAP. Unless an external ICAP arbiter is used to drive these signals, the cap_gnt signal should be High and cap_rel should be Low.

During the Initialization state, status_initialization is asserted High. Initialization includes some internal housekeeping, in addition to directly observable events such as the generation of an initialization report on the Monitor Interface. The specific activities include:

  • First readback cycle during which the frame-level ECC checksums are computed.
  • Second readback cycle during which the device-level CRC checksum is computed.

At the completion of initialization, the controller transitions to the Observation, Detect only, or Idle state depending on the IP mode.