For UltraScale devices, SEM IP and Partial Reconfiguration (PR) are supported only when monolithic devices are used. When using stacked silicon interconnect (SSI) devices, SEM IP and PR are not supported.
For UltraScale+ devices, SEM IP and Partial Reconfiguration is supported with both monolithic and SSI devices.
Although the implementation of a design that contains SEM IP and Partial Reconfiguration is outside the scope of this document, the following can provide guidance: see Demonstration of Soft Error Mitigation IP and Partial Reconfiguration Capability on Monolithic Devices (XAPP1261). While XAPP1261 demonstrates compatibility of SEM IP and monolithic devices, the same guidance can be used for UltraScale+ SSI devices.