Demonstration on Communicating with the SEM Controller through the UART Interface - 3.1 English

UltraScale Architecture Soft Error Mitigation Controller LogiCORE IP Product Guide (PG187)

Document ID
PG187
Release Date
2023-11-08
Version
3.1 English

This section gives a step-by-setup instruction on how to perform a basic error injection and the expected status output from the SEM controller by using the terminal emulator to communicate with the SEM controller through the UART Interface. All commands are issued and status received using the terminal emulator. The instructions goes through the Initialization report, Status report, Idle versus Observation states, Error Injection, and Correction report. This example assumes that the IP is configured in the Mitigation and Testing mode with Classification disabled which is the default configuration of the Vivado Integrated Design Environment (IDE).

To understand how the IP transitions through each state during this example, see the state diagram in Figure 1. The list of commands (and its format) and reports used in this demonstration can be found in UART Interface Messages and UART Interface Commands of this document.

When the generated bitstream is programmed onto the device, an initialization report is received in the terminal emulator. The report looks like the following:

SEM_ULTRA_V3_1         Name and version
SC 01                State transition to Initialization state
FS 04                Core Configuration Information
AF 01                Additional Core Configuration Information
ICAP OK              ICAP Available
RDBK OK              Status: Readback Active
INIT OK              Status: Completed Setup
SC 02                State transition to Observation
O>                   Observation prompt

Now, the controller has finished initialization and is observing the FPGA configuration system for indication of error conditions. The status_observation signal is asserted in the VIO window.

To emulate an error occurring in the configuration memory, you have to transition the controller to the Idle state. You can do this by sending the command to the UART interface from the terminal emulator:

O>         I Enter Idle Command
SC 00         State change into Idle state
I>            Idle prompt

Now, all the status flags (all status_* ignoring status_essential and status_uncorrectable ) are deasserted indicating that the controller is in Idle state.

When the controller enters Idle state, it disables the built-in configuration memory scan and checks. Available commands in this state are shown in Table 1.

If a Full status report is requested by sending an "S" through the UART interface, you receive the following output:

I> S         Status request command ("S")
SN 00         SLR number
SC 00         Current State
FC 00         Current Flags
RI 00         Reserved Information
MF 00006643   Maximum Linear Frame Count
TS XXXXXXXX   Timestamp
TB XXXXXXXX   Table Base
CB XXXXXXXX   Classification Base
CL 001        Classification Level
I>            Idle Prompt

After the Full status report is complete, the Idle prompt returns to receive the next command.

To emulate an error occurring in the configuration memory, you can perform an error injection. In general, AMD recommends performing an error injection in the ECC word of the frame. An error injection in the ECC word does not impact the configured design but enables you to observe what happens when a configuration error is found.

AMD also recommends that you query the content of the frame in which the error is injected into, before and after injecting errors. This enables you to confirm that the error injection is successful in altering the configuration memory and whether the controller detects and corrects the injected errors.

In this example, inject an error in Frame 0, Word 61, and Bit 0 which is a bit in the ECC word for an UltraScale device.

First, perform a Query command to read the content of frame 0.

I> Q C000000000         Query command using LFA
{61 lines of 00000000}
00000000         Location we will inject an error
{61 lines of 00000000}
I>

Now, perform the error injection at Frame 0, Word 61, and Bit 0.

I> N         C0000007A0 Error injection command using LFA
SC 10         State transition to Error Injection
SC 00         State transition to Idle
I>            Idle Prompt

When the IP performs error injection, it briefly enters the Error Injection state, asserting the status_injection signal during that time.

Finally, perform a Query command again to ensure an error has been introduced at the chosen location.

I> Q         C000000000 Query command by LFA
{61 lines of 00000000}
00000001         Location we have injected an error
{61 lines of 00000000}
I>

Because the bit targeted by the error injection command has changed, it is confirmed that the error injection was successful.

To demonstrate error detection and correction capability of the controller, you need to command the controller to re-enter the Observation state and resume observing the FPGA configuration system for indication of error conditions.

To enter the Observation state, issue the following command:

I> O                 Enter Observation Command
SC 02                 State transition to Observation
O>                    Observation prompt
RI XX                 Reserved information
SC 04                 State transition to Correction
ECC ECC               error detected
TS 0000245D           Timestamp
PA 0000000            PFA of detected error
LA 0000000            LFA of detected error
COR Error             correction report begins
WD 3D BT 00           Corrected word and bit values
END                   Error correction report end
FC 00                 Flag updated with correctability
SC 08                 State transition to Classification
FC 40                 Flag updated with essentialness (if classification is disabled, it is always essential)
SC 02                 State transition to Observation
O>                    Observation prompt

Observe that after transition to the Observation state, the controller subsequently detected and reported the error, indicated by the error detection and correction report generated in the Correction state.

After completing the error correction, the controller transitions to the Classification state before transitioning back into the Observation state and resumes observing the FPGA configuration system for further indication of error conditions.

Note: If the Classification feature is disabled, the flag always indicates that the error is essential.

The Flag Change update provides two pieces of information:

  • Correctability (reflected on status_uncorrectable )
  • Essentialness (reflected on status_essential ).

Correctability gets updated after the correction report ends and essentialness gets updated before it transitions out of the Classification state. Until either of those stages are hit again, the Flag Change variable value continues to remain the same. See Table 1 to understand the different Flag Change Values and their corresponding meanings.

Note: Each State and Flag Change reported on the UART interface are reflected on the status_* signals in the VIO window.

For more information on emulating the occurrence of errors in the configuration memory, see Error Injection Guidance.

In this demonstration, all commands to the IP were given through the terminal emulator to the UART Interface. The same commands can be executed using the Command Interface through the VIO window. Each correctly given command through this interface is echoed on the UART Interface resulting in the same status and reports shown above. For more information on how to provide commands through the Command Interface, see Command Interface.