Test Bench - 3.1 English - PG187

UltraScale Architecture Soft Error Mitigation Controller LogiCORE IP Product Guide (PG187)

Document ID
PG187
Release Date
2025-05-29
Version
3.1 English

This chapter contains information about the test bench provided in the AMD Vivado™ Design Suite.

A simulation test harness is provided with the example design. This enables functional and timing simulation of designs that include an AMD UltraScale™ architecture SEM controller using standard AMD simulation flows. However, it is not possible to observe the SEM controller behaviors in simulation. Hardware-based evaluation is required.

For comprehensive information about Vivado simulation components and using supported third-party tools, see the Vivado Design Suite User Guide: Logic Simulation (UG900).