Test Bench - 3.1 English

UltraScale Architecture Soft Error Mitigation Controller LogiCORE IP Product Guide (PG187)

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3.1 English

This chapter contains information about the test bench provided in the AMD Vivado™ Design Suite.

A simulation test harness is provided with the example design. This enables functional and timing simulation of designs that include the AMD UltraScale™ architecture SEM controller using standard AMD simulation flows. However, it is not possible to observe the SEM controller behaviors in simulation. Hardware-based evaluation is required.