Controller Clock Period - 3.1 English

UltraScale Architecture Soft Error Mitigation Controller LogiCORE IP Product Guide (PG187)

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3.1 English

The controller clock period is set by the Clock Period field. The error mitigation time decreases as the controller clock period decreases or as frequency increases. Therefore, the clock period should be as small as practical. The dialog box warns if the desired period exceeds the capability of the target device.

For designs that require a data retrieval interface to fetch external data for error classification, an additional consideration exists. The example design implements an external memory interface that is synchronous to the controller. The controller clock frequency therefore also determines the external memory cycle time. The external memory system must be analyzed to determine its minimum cycle time, as it can limit the maximum controller clock frequency.

Instructions on how to perform this analysis are located in Interfaces. However, this analysis requires timing data from implementation results. Therefore, AMD recommends the following:

  1. Generate the solution using the desired frequency or clock period setting.
  2. Extract the required timing data from the implementation results.
  3. Complete the timing budget analysis to determine maximum frequency.
  4. Re-generate the solution with a frequency at or below the calculated maximum frequency of operation.
Note: When an evaluation board is targeted, the default Controller Clock Period is automatically selected to a specific clock frequency based pinout delivered in the example design.