XilFPGA APIs for Versal ACAPs and Zynq UltraScale+ MPSoCs - 2021.1 English

Xilinx Standalone Library Documentation OS and Libraries Document Collection (UG643)
Document ID
UG643
Release Date
2021-06-16
Version
2021.1 English

The following APIs are supported by Versal ACAPs and Zynq UltraScale+ MPSoCs.

Table 1. Quick Function Reference
Type Name Arguments
u32 XFpga_Initialize
  • XFpga * InstancePtr
u32 XFpga_PL_BitStream_Load
  • XFpga * InstancePtr
  • UINTPTR BitstreamImageAddr
  • UINTPTR AddrPtr_Size
  • u32 Flags
u32 XFpga_BitStream_Load
  • XFpga * InstancePtr
  • UINTPTR BitstreamImageAddr
  • UINTPTR KeyAddr
  • u32 Size
  • u32 Flags
u32 XFpga_PL_ValidateImage
  • XFpga * InstancePtr
  • UINTPTR BitstreamImageAddr
  • UINTPTR AddrPtr_Size
  • u32 Flags
u32 XFpga_ValidateImage
  • XFpga * InstancePtr
  • UINTPTR BitstreamImageAddr
  • UINTPTR KeyAddr
  • u32 Size
  • u32 Flags
u32 XFpga_PL_Preconfig
  • XFpga * InstancePtr
u32 XFpga_PL_Write
  • XFpga * InstancePtr
  • UINTPTR BitstreamImageAddr
  • UINTPTR AddrPtr_Size
  • u32 Flags
u32 XFpga_Write_Pl
  • XFpga * InstancePtr
  • UINTPTR BitstreamImageAddr
  • UINTPTR KeyAddr
  • u32 Size
  • u32 Flags
u32 XFpga_PL_PostConfig
  • XFpga * InstancePtr