Loading an Authenticated and Encrypted Bitstream using DDR Memory Controller - 2021.1 English

Xilinx Standalone Library Documentation OS and Libraries Document Collection (UG643)

Document ID
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2021.1 English
The software workflow for authenticating bitstream is as follows:
  1. XilFPGA identifies DDR-secure bitstream image base address.
  2. XilFPGA calculates hash for the first 8 MB block.
  3. XilFPGA authenticates the 8 MB block while stored in the external DDR memory.
  4. If Authentication is successful, XilFPGA transmits data to PCAP via DMA (for unencrypted Bitstream) or AES (if encryption is enabled).
  5. Repeats steps 1 through 4 for all the blocks of bitstream.