In Ultrascale the following GPIO pins are used for connecting MASTER_JTAG pins to access eFUSE. These can be changed depending on your hardware.The table below shows the GPIO pins used for PL MASTER JTAG signals.
| Master JTAG Signal | Default PIN Number |
|---|---|
| XSK_EFUSEPL_AXI_GPIO_JTAG_TDO | 0 |
| XSK_EFUSEPL_AXI_GPIO_HWM_READY | 0 |
| XSK_EFUSEPL_AXI_GPIO_HWM_END | 1 |
| XSK_EFUSEPL_AXI_GPIO_JTAG_TDI | 2 |
| XSK_EFUSEPL_AXI_GPIO_JTAG_TMS | 1 |
| XSK_EFUSEPL_AXI_GPIO_JTAG_TCK | 2 |
| XSK_EFUSEPL_AXI_GPIO_HWM_START | 3 |