Arm Cortex-A53 32-bit Processor Boot Code - 2021.1 English

Xilinx Standalone Library Documentation OS and Libraries Document Collection (UG643)

Document ID
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2021.1 English

The boot.S file contains a minimal set of code for transferring control from the processor reset location to the start of the application. The boot code performs minimum configuration which is required for an application to run starting from processor reset state of the processor. Below is a sequence illustrating what all configuration is performed before control reaches to main function.

  1. Program vector table base for exception handling
  2. Invalidate instruction cache, data cache and TLBs
  3. Program stack pointer for various modes (IRQ, FIQ, supervisor, undefine, abort, system)
  4. Program counter frequency
  5. Configure MMU with short descriptor translation table format and program base address of translation table
  6. Enable data cache, instruction cache and MMU
  7. Transfer control to _start which clears BSS sections and runs global constructor before jumping to main application

The translation_table.S contains a static page table required by MMU for cortex-A53. This translation table is flat mapped (input address = output address) with default memory attributes defined for Zynq Ultrascale+ architecture. It utilizes short descriptor translation table format with each section defining 1 MB of memory.

The overview of translation table memory attributes is described below.

Memory Range Definition in Translation Table
DDR 0x00000000 - 0x7FFFFFFF Normal write-back Cacheable
PL 0x80000000 - 0xBFFFFFFF Strongly Ordered
QSPI, lower PCIe 0xC0000000 - 0xEFFFFFFF Device Memory
Reserved 0xF0000000 - 0xF7FFFFFF Unassigned
STM Coresight 0xF8000000 - 0xF8FFFFFF Device Memory
GIC 0xF9000000 - 0xF90FFFFF Device memory
Reserved 0xF9100000 - 0xFCFFFFFF Unassigned
FPS, LPS slaves 0xFD000000 - 0xFFBFFFFF Device memory
CSU, PMU 0xFFC00000 - 0xFFDFFFFF Device Memory
TCM, OCM 0xFFE00000 - 0xFFFFFFFF Normal write-back cacheable
Note: For DDR in region 0x00000000 - 0x7FFFFFFF, a system where DDR is less than 2 GB, region after DDR and before PL is marked as undefined/reserved in translation table. In region 0xFFC00000 - 0xFFDFFFFF, it contains CSU and PMU memory which are marked as Device since it is less than 1 MB and falls in a region with device memory.