Performance - 2021.1 English

Xilinx Standalone Library Documentation OS and Libraries Document Collection (UG643)

Document ID

UG643

Release Date

2021-06-16

Version

2021.1 English

Performance metrics for the XilSEM library are derived from silicon specifications and direct measurement and are for budgetary purposes only. Actual performance might vary.

Table 1. Performance Metrics for the Configuration RAM
Device and Conditions	Initialization	Complete Scan Time	Correctable ECC Error Handling	Uncorrectable CRC Error Handling	Other Uncorrectable Error Handling
XCVC1902 PMC = 320 MHz CFU = 400 MHz	SW ECC: 18.1 ms HW ECC: 36.2 ms	13.6 ms (with 149682 CRAM frames)	55 us	16 us	49 us
XCVM1802 PMC = 320 MHz CFU = 400 MHz	SW ECC: 18.1 ms HW ECC: 36.2 ms	13.6 ms (with 149682 CRAM frames)	55 us	16 us	49 us

Table 2. Performance Metrics for NPI Registers
Device and Conditions	Initialization	Complete Scan Time	Uncorrectable SHA Error Handling	Other Uncorrectable Error Handling
XCVC1902 PMC = 320 MHz CFU = 400 MHz	SW SHA: 23 ms HW SHA: 23 ms	14.6 ms (with 900+ NPI slaves)	Pending Characterization	Pending Characterization
XCVM1802 PMC = 320 MHz CFU = 420 MHz	Pending Characterization	Pending Characterization	Pending Characterization	Pending Characterization

Error detection latency is the major component of the total error mitigation latency. Error detection latency is a function of the device size and the underlying clock signals driving the processes involved, as these determine the Complete Scan time. It is also a function of the type of error and the relative position of the error with respect to the position of the scan process, at the time the error occurs. The error detection latency can be bounded as follows:

Maximum error detection latency for detection by ECC is one Complete Scan Time
- This represents a highly unlikely case when an error at a given location occurs directly “behind” the scan process.
- It will take one Complete Scan Time for the scan process to return to the error location at which time it will detect it.
Maximum error detection latency for detection by CRC or SHA is 2.0 × Complete Scan Time
- This represents an extremely unlikely case when an error occurs directly “behind” the scan process and is located at the scan start location (where the checksum accumulation begins at each scan).
- It will take one Complete Scan Time for the scan process to complete the current checksum accumulation (which will pass) and then a second Complete Scan Time to complete a checksum accumulation which includes the error (which will fail).