User Side AXI4-Stream Interface - 3.1 English - PG203

UltraScale+ Devices Integrated 100G Ethernet Subsystem LogiCORE IP Product Guide (PG203)

Document ID
PG203
Release Date
2024-07-17
Version
3.1 English

For the AXI4-Stream interface, AXIS to LBUS converter at TX path and LBUS to AXIS converter at RX path are incorporated. These modules convert the 128-bit data of four segments of LBUS interface into a 512-bit AXI4-Stream data for user side interface.

Figure 1. LBUS to AXI4-Stream Core
Page-1 Process.439 Process.2 GT GT Sheet.3 Sheet.4 Sheet.5 Sheet.6 Sheet.7 TX AXIS TX AXIS Process.27 AXIS to LBUS AXIS to LBUS Sheet.9 cmac_wrapper cmac_wrapper Process.31 LBUS to AXIS LBUS to AXIS Process.33 cmac_top cmac_top Sheet.12 Sheet.13 Sheet.14 RX AXIS RX AXIS Sheet.15 Sheet.16 Sheet.17 TX LBUS TX LBUS Sheet.18 Sheet.19 Sheet.20 RX LBUS RX LBUS Sheet.21 Sheet.22 Sheet.23 X22474-032919 X22474-032919
Note: For more details on the AXI4-Stream interface and frame transmission mechanism, refer to the Transmit AXI4-Stream Interface and Receive AXI4-Stream Interface section of 10G/25G High Speed Ethernet Subsystem Product Guide (PG210).