- Added integrated Reed Solomon-Forward Error Correction (RS-FEC) block including
the Transcode Bypass mode.
- Added support for programmable inter-packet gap (IPG).
- Added support for custom preambles.
- Added support for overclocking. See the
Virtex
UltraScale+ FPGA Data Sheet: DC and AC Switching
Characteristics (DS923)
- CMAC CAUI-10 10x12.5G in -2 and above.
- CMAC CAUI-4 with RS-FEC 4x31.25G in -3 and above.
- Added registers on all the input for better timing.
- Added behavioral code for the standard cells for secure IP to help speed up
simulation.