PCS Lane Multiplexing - 3.1 English - PG203

UltraScale+ Devices Integrated 100G Ethernet Subsystem LogiCORE IP Product Guide (PG203)

Document ID
PG203
Release Date
2024-07-17
Version
3.1 English

Between the CAUI-10 and CAUI-4 modes, the PCS multiplexer blocks combine and distribute the PMD lanes from the SerDes to the internal PCS lane logic. The following figure illustrates the multiplexing and demultiplexing function contained in the RX and TX PCS multiplexer blocks for the SerDes interfaces which are 80 bits wide. The lower 32 bits are used in CAUI-10 mode.

Figure 1. PCS Multiplexing in CAUI-10 and CAUI-4 Modes
UltraScale Architecture Integrated Block for 100G Ethernet (CMAC) Page-1 Custom 2 Custom 2.3 Standard Arrow.47 Standard Arrow.5 Standard Arrow.6 Standard Arrow.7 Standard Arrow.8 Standard Arrow.9 Standard Arrow.10 Sheet.11 Sheet.12 Sheet.13 PCS Lane 0 (16b) PCS Lane 0 (16b) Sheet.14 PCS Lane 1 (16b) PCS Lane 1 (16b) Sheet.15 PCS Lane 2 (16b) PCS Lane 2 (16b) Sheet.16 PCS Lane 3 (16b) PCS Lane 3 (16b) Sheet.17 PCS Lane 4 (16b) PCS Lane 4 (16b) Sheet.18 CAUI mode 2:1 Multiplexing CAUI mode 2:1 Multiplexing Sheet.19 CAUI-4 mode 5:1 Multiplexing CAUI-4 mode 5:1 Multiplexing Sheet.20 CAUI-10 TX PMD Lane 0 (32b) CAUI-10TX PMD Lane 0(32b) Sheet.21 CAUI-4 TX PMD Lane 0 (80b) CAUI-4TX PMD Lane 0(80b) Custom 2.22 Custom 2.23 Standard Arrow.24 Standard Arrow.25 Standard Arrow.26 Standard Arrow.27 Standard Arrow.28 Standard Arrow.29 Standard Arrow.30 Sheet.31 Sheet.32 Sheet.33 PCS Lane 0 (16b) PCS Lane 0 (16b) Sheet.34 PCS Lane 1 (16b) PCS Lane 1 (16b) Sheet.35 PCS Lane 2 (16b) PCS Lane 2 (16b) Sheet.36 PCS Lane 3 (16b) PCS Lane 3 (16b) Sheet.37 PCS Lane 4 (16b) PCS Lane 4 (16b) Sheet.38 CAUI mode 1:2 De-multiplexing CAUI mode 1:2 De-multiplexing Sheet.39 CAUI-4 mode 1:5 De-multiplexing CAUI-4 mode 1:5 De-multiplexing Sheet.40 CAUI-10 RX PMD Lane 0 (32b) CAUI-10RX PMD Lane 0(32b) Sheet.41 CAUI-4 RX PMD Lane 0 (80b) CAUI-4RX PMD Lane 0(80b) Sheet.42 TX PCS Lane Muxing TX PCS Lane Muxing Sheet.43 RX PCS Lane De-multiplexing RX PCS Lane De-multiplexing Sheet.44 X17167-022117 X17167-022117

The preceding pattern is repeated for the other three 80-bit SerDes interfaces.

Each 80-bit SerDes interface is actually composed of a 16-bit group and a 64-bit group. The mapping of these two groups onto the 80-bit interface is illustrated in the following figures for RX and TX respectively.

Figure 2. RX GTY Mapping
Note: The connectivity between the 100G Ethernet IP RX SerDes data interface to the GTY transceiver RX datapath for CAUI-10 and CAUI-4/100GAUI-4 operation is taken care of in the 100G Ethernet IP core.
Figure 3. TX GTY Mapping
Note: The connectivity between the 100G Ethernet IP TX SerDes data interface to the GTY transceiver TX datapath for CAUI-10 and CAUI-4/100GAUI-4 operation is taken care of in the 100G Ethernet IP core.
Figure 4. 100GAUI-2 TX GTM Mapping
Page-1 Sheet.1 Sheet.2 tx_serdes_data_3[63:0] tx_serdes_data_3[63:0] Sheet.3 Sheet.4 tx_serdes_alt_data_3[15:0] tx_serdes_alt_data_3[15:0] Sheet.5 Sheet.6 internal_tx_serdes_data_3[79:0] internal_tx_serdes_data_3[79:0] Sheet.7 CH1_TX_Data[159:0] CH1_TX_Data[159:0] Sheet.9 CH0_TX_Data[159:0] CH0_TX_Data[159:0] Sheet.10 To GTM To GTM Sheet.11 From CMAC From CMAC Sheet.12 Sheet.13 Concat Concat Sheet.14 0 0 Sheet.15 1 1 Sheet.16 Lane_3 Lane_3 Sheet.17 Sheet.18 tx_serdes_data_2[63:0] tx_serdes_data_2[63:0] Sheet.19 Sheet.20 tx_serdes_alt_data_2[15:0] tx_serdes_alt_data_2[15:0] Sheet.21 Sheet.22 internal_tx_serdes_data_2[79:0] internal_tx_serdes_data_2[79:0] Sheet.23 Concat Concat Sheet.24 0 0 Sheet.25 1 1 Sheet.26 Lane_2 Lane_2 Sheet.27 Sheet.28 tx_serdes_data_1[63:0] tx_serdes_data_1[63:0] Sheet.29 Sheet.30 tx_serdes_alt_data_1[15:0] tx_serdes_alt_data_1[15:0] Sheet.31 Sheet.32 internal_tx_serdes_data_1[79:0] internal_tx_serdes_data_1[79:0] Sheet.33 Concat Concat Sheet.34 0 0 Sheet.35 1 1 Sheet.36 Lane_1 Lane_1 Sheet.37 Sheet.38 tx_serdes_data_0[63:0] tx_serdes_data_0[63:0] Sheet.39 Sheet.40 tx_serdes_alt_data_0[15:0] tx_serdes_alt_data_0[15:0] Sheet.41 Sheet.42 internal_tx_serdes_data_0[79:0] internal_tx_serdes_data_0[79:0] Sheet.43 Concat Concat Sheet.44 0 0 Sheet.45 1 1 Sheet.46 Lane_0 Lane_0 Sheet.47 Sheet.48 Sheet.49 Sheet.50 Sheet.51 Sheet.52 {data_3[79:0],data_2[79:0]} {data_3[79:0],data_2[79:0]} Sheet.53 {data_1[79:0],data_0[79:0]} {data_1[79:0],data_0[79:0]} Sheet.54 320b @332.03125 MHz 320b @332.03125 MHz Sheet.55 106.250 Gb/s 106.250 Gb/s Sheet.56 320b @322.2656 MHz 320b @322.2656 MHz Sheet.57 103.125 Gb/s 103.125 Gb/s Sheet.58 X21781-102318 X21781-102318
Figure 5. 100GAUI-2 RX GTM Mapping
Page-1 Sheet.1 Sheet.2 rx_serdes_data_3[63:0] rx_serdes_data_3[63:0] Sheet.3 Sheet.4 rx_serdes_alt_data_3[15:0] rx_serdes_alt_data_3[15:0] Sheet.5 Sheet.6 internal_rx_serdes_data_3[79:0] internal_rx_serdes_data_3[79:0] Sheet.7 CH1_RX_Data[159:0] CH1_RX_Data[159:0] Sheet.9 CH0_RX_Data[159:0] CH0_RX_Data[159:0] Sheet.10 From GTM From GTM Sheet.11 To CMAC To CMAC Sheet.12 Sheet.13 Concat Concat Sheet.14 0 0 Sheet.15 1 1 Sheet.16 Lane_3 Lane_3 Sheet.17 Sheet.18 rx_serdes_data_2[63:0] rx_serdes_data_2[63:0] Sheet.19 Sheet.20 rx_serdes_alt_data_2[15:0] rx_serdes_alt_data_2[15:0] Sheet.21 Sheet.22 internal_rx_serdes_data_2[79:0] internal_rx_serdes_data_2[79:0] Sheet.23 Concat Concat Sheet.24 0 0 Sheet.25 1 1 Sheet.26 Lane_2 Lane_2 Sheet.27 Sheet.28 rx_serdes_data_1[63:0] rx_serdes_data_1[63:0] Sheet.29 Sheet.30 rx_serdes_alt_data_1[15:0] rx_serdes_alt_data_1[15:0] Sheet.31 Sheet.32 internal_rx_serdes_data_1[79:0] internal_rx_serdes_data_1[79:0] Sheet.33 Concat Concat Sheet.34 0 0 Sheet.35 1 1 Sheet.36 Lane_1 Lane_1 Sheet.37 Sheet.38 rx_serdes_data_0[63:0] rx_serdes_data_0[63:0] Sheet.39 Sheet.40 rx_serdes_alt_data_0[15:0] rx_serdes_alt_data_0[15:0] Sheet.41 Sheet.42 internal_rx_serdes_data_0[79:0] internal_rx_serdes_data_0[79:0] Sheet.43 Concat Concat Sheet.44 0 0 Sheet.45 1 1 Sheet.46 Lane_0 Lane_0 Sheet.47 Sheet.48 Sheet.49 Sheet.50 Sheet.51 Sheet.52 {data_3[79:0],data_2[79:0]} {data_3[79:0],data_2[79:0]} Sheet.53 {data_1[79:0],data_0[79:0]} {data_1[79:0],data_0[79:0]} Sheet.54 320b @332.03125 MHz 320b @332.03125 MHz Sheet.55 106.250 Gb/s 106.250 Gb/s Sheet.56 320b @322.2656 MHz 320b @322.2656 MHz Sheet.57 103.125 Gb/s 103.125 Gb/s Sheet.58 X21782-102318 X21782-102318
Figure 6. CAUI-4 TX GTM Mapping
Page-1 Sheet.1 Sheet.2 Sheet.3 Sheet.4 Sheet.5 [79:78] [79:78] Sheet.6 Sheet.7 [69:68] [69:68] Sheet.8 Sheet.9 [59:58] [59:58] Sheet.10 Sheet.11 [49:48] [49:48] Sheet.12 Sheet.13 [39:38] [39:38] Sheet.14 Sheet.15 [29:28] [29:28] Sheet.16 Sheet.17 [19:18] [19:18] Sheet.18 Sheet.19 [9:8] [9:8] Sheet.20 Sheet.21 [7:0] [7:0] Sheet.22 Sheet.23 [17:10] [17:10] Sheet.24 Sheet.25 [27:20] [27:20] Sheet.26 Sheet.27 [37:30] [37:30] Sheet.28 Sheet.29 [47:40] [47:40] Sheet.30 Sheet.31 [57:50] [57:50] Sheet.32 Sheet.33 [67:60] [67:60] Sheet.34 Sheet.35 [77:70] [77:70] Sheet.36 Sheet.37 Sheet.38 Sheet.39 tx_serdes_data_3[63:0] tx_serdes_data_3[63:0] Sheet.40 Sheet.41 Sheet.42 [7:0] [7:0] Sheet.43 [15:8] [15:8] Sheet.44 [23:16] [23:16] Sheet.45 [31:24] [31:24] Sheet.46 [39:32] [39:32] Sheet.47 [47:40] [47:40] Sheet.48 [55:48] [55:48] Sheet.49 [63:56] [63:56] Sheet.50 [1:0] [1:0] Sheet.51 [3:2] [3:2] Sheet.52 [5:4] [5:4] Sheet.53 [7:6] [7:6] Sheet.54 [9:8] [9:8] Sheet.55 [11:10] [11:10] Sheet.56 [13:12] [13:12] Sheet.57 [15:14] [15:14] Sheet.58 Sheet.59 Sheet.60 Sheet.61 tx_serdes_alt_data_3[15:0] tx_serdes_alt_data_3[15:0] Sheet.62 Sheet.63 int_tx_serdes_data_3[79:0] int_tx_serdes_data_3[79:0] Sheet.64 Sheet.65 int_tx_serdes_data_2[79:0] int_tx_serdes_data_2[79:0] Sheet.66 Sheet.67 int_tx_serdes_data_1[79:0] int_tx_serdes_data_1[79:0] Sheet.68 Sheet.69 int_tx_serdes_data_0[79:0] int_tx_serdes_data_0[79:0] Sheet.70 Lane_3 Lane_3 Sheet.71 Lane_2 Lane_2 Sheet.72 Lane_1 Lane_1 Sheet.73 Lane_0 Lane_0 Sheet.74 DUAL1_CH1_TX_Data[63:0] DUAL1_CH1_TX_Data[63:0] Sheet.76 tx_serdes_data_3[63:0] tx_serdes_data_3[63:0] Sheet.77 To GTM To GTM Sheet.78 From CMAC From CMAC Sheet.79 256b @402.8320 MHz 256b @402.8320 MHz Sheet.80 103.125 Gb/s 103.125 Gb/s Sheet.81 DUAL1_CH0_TX_Data[63:0] DUAL1_CH0_TX_Data[63:0] Sheet.82 tx_serdes_data_2[63:0] tx_serdes_data_2[63:0] Sheet.83 DUAL0_CH1_TX_Data[63:0] DUAL0_CH1_TX_Data[63:0] Sheet.84 tx_serdes_data_1[63:0] tx_serdes_data_1[63:0] Sheet.85 DUAL0_CH0_TX_Data[63:0] DUAL0_CH0_TX_Data[63:0] Sheet.86 tx_serdes_data_0[63:0] tx_serdes_data_0[63:0] Sheet.183 320b @322.2656 MHz 320b @322.2656 MHz Sheet.184 103.125 Gb/s 103.125 Gb/s Sheet.185 TX Gearbox TXGearbox Sheet.186 Sheet.187 TX Gearbox TXGearbox Sheet.188 Sheet.189 TX Gearbox TXGearbox Sheet.190 Sheet.191 TX Gearbox TXGearbox Sheet.192 Sheet.87 X21783-031419 X21783-031419
Figure 7. CAUI-4 RX GTM Mapping
Page-1 Sheet.1 Sheet.2 [15:14] [15:14] Sheet.3 Sheet.4 [63:56] [63:56] Sheet.5 Sheet.6 [13:12] [13:12] Sheet.7 Sheet.8 [55:48] [55:48] Sheet.9 Sheet.10 [11:10] [11:10] Sheet.11 Sheet.12 [47:40] [47:40] Sheet.13 Sheet.14 [9:8] [9:8] Sheet.15 Sheet.16 [39:32] [39:32] Sheet.17 Sheet.18 [7:0] [7:0] Sheet.19 Sheet.20 [1:0] [1:0] Sheet.21 Sheet.22 [15:8] [15:8] Sheet.23 Sheet.24 [3:2] [3:2] Sheet.25 Sheet.26 [23:16] [23:16] Sheet.27 Sheet.28 [5:4] [5:4] Sheet.29 Sheet.30 [31:24] [31:24] Sheet.31 Sheet.32 [7:6] [7:6] Sheet.33 Sheet.34 rx_serdes_data_3[63:0] rx_serdes_data_3[63:0] Sheet.35 Sheet.36 Sheet.37 Sheet.38 Sheet.39 Sheet.40 [79:78] [79:78] Sheet.41 [77:70] [77:70] Sheet.42 [69:68] [69:68] Sheet.43 [67:60] [67:60] Sheet.44 [59:58] [59:58] Sheet.45 [57:50] [57:50] Sheet.46 [49:48] [49:48] Sheet.47 [47:40] [47:40] Sheet.48 [7:0] [7:0] Sheet.49 [9:8] [9:8] Sheet.50 [17:10] [17:10] Sheet.51 [19:18] [19:18] Sheet.52 [27:20] [27:20] Sheet.53 [29:28] [29:28] Sheet.54 [37:30] [37:30] Sheet.55 [39:38] [39:38] Sheet.56 Sheet.57 rx_serdes_alt_data_3[15:0] rx_serdes_alt_data_3[15:0] Sheet.58 Sheet.59 Sheet.60 Sheet.61 Sheet.62 Sheet.63 Sheet.64 Sheet.65 Sheet.66 Sheet.67 Sheet.68 Sheet.69 Sheet.70 Sheet.71 int_rx_serdes_data_3[79:0] int_rx_serdes_data_3[79:0] Sheet.72 Sheet.73 int_rx_serdes_data_2[79:0] int_rx_serdes_data_2[79:0] Sheet.74 Sheet.75 int_rx_serdes_data_1[79:0] int_rx_serdes_data_1[79:0] Sheet.76 Sheet.77 int_rx_serdes_data_0[79:0] int_rx_serdes_data_0[79:0] Sheet.78 Lane_3 Lane_3 Sheet.79 Lane_2 Lane_2 Sheet.80 Lane_1 Lane_1 Sheet.81 Lane_0 Lane_0 Sheet.83 From GTM From GTM Sheet.84 Sheet.85 Sheet.87 256b @402.8320 MHz 256b @402.8320 MHz Sheet.88 103.125 Gb/s 103.125 Gb/s Sheet.89 DUAL1_CH1_RX_Data[63:0] DUAL1_CH1_RX_Data[63:0] Sheet.90 rx_serdes_data_3[63:0] rx_serdes_data_3[63:0] Sheet.91 DUAL1_CH0_RX_Data[63:0] DUAL1_CH0_RX_Data[63:0] Sheet.92 rx_serdes_data_2[63:0] rx_serdes_data_2[63:0] Sheet.93 DUAL0_CH1_RX_Data[63:0] DUAL0_CH1_RX_Data[63:0] Sheet.94 rx_serdes_data_1[63:0] rx_serdes_data_1[63:0] Sheet.95 DUAL0_CH0_RX_Data[63:0] DUAL0_CH0_RX_Data[63:0] Sheet.96 rx_serdes_data_0[63:0] rx_serdes_data_0[63:0] Sheet.203 To CMAC To CMAC Sheet.204 320b @322.2656 MHz 320b @322.2656 MHz Sheet.205 103.125 Gb/s 103.125 Gb/s Sheet.206 RX Gearbox RXGearbox Sheet.207 Sheet.208 RX Gearbox RXGearbox Sheet.209 Sheet.210 RX Gearbox RXGearbox Sheet.211 Sheet.212 RX Gearbox RXGearbox Sheet.213 Sheet.97 X21784-031419 X21784-031419