STAT_RX_BAD_FCS[2:0] - 3.1 English

UltraScale+ Devices Integrated 100G Ethernet Subsystem Product Guide (PG203)

Document ID
Release Date
3.1 English

When this signal is a value of 1, it indicates that the error detection logic has identified a mismatch between the expected and received value of CRC32 in the received packet.

When a CRC32 error is detected, the received packet is marked as containing an error and it is sent with RX_ERROUT asserted during the last transfer (the cycle with RX_EOPOUT asserted), unless CTL_RX_IGNORE_FCS is asserted. This signal is asserted for one clock period each time a CRC32 error is detected.