Notes - 3.1 English

UltraScale+ Devices Integrated 100G Ethernet Subsystem LogiCORE IP Product Guide (PG203)

Document ID
PG203
Release Date
2024-07-17
Version
3.1 English
  • Altering the value of CTL_TX_VL_LENGTH_MINUS1 and CTL_RX_VL_LENGTH_MINUS1 from the default value of 0x3FFF will violate the IEEE 802.3 specification.
  • Decreasing the AM spacing will result in less than 100G Ethernet bandwidth being available on the link.
  • This change can be made only in simulation. For a design to work in hardware, the default value of 0x3FFF must be used.
  • Full-rate simulation without the SIM_SPEED_UP option should still be run.
  • SIM_SPEED_UP is available only when running RTL simulations. The option is not available for post-synthesis or post-implementation simulations.