Stages and Status Signals - 3.1 English

UltraScale+ Devices Integrated 100G Ethernet Subsystem LogiCORE IP Product Guide (PG203)
Document ID
PG203
Release Date
2024-07-17
Version
3.1 English
  1. At the start of AN, there is a TX disable state where no data is seen to ensure link is down on both sides. The stat_an_start_tx_disable signal toggles for one cycle to indicate the start of this stage.
  2. Following the TX disable state, AN information is exchanged. During this stage stat_an_rxcdrhold is High. The Stat_an_lp_autoneg_able and stat_an_lp_ability_valid signals toggle High for one clock cycle to indicate when stat_an_lp* information is valid.
  3. Stat_an_start_an_good_check toggles High for one cycle at the start of link training. The Stat_an_rxcdrhold signal is de-asserted and gtwiz_reset_rx_datapath toggled.

    After the link training starts, there is a 500 ms timer to train and block lock/link up in mission mode/normal PCS operation to complete or AN restarts.

  4. The stat_lt_frame_lock signal goes High and the stat_lt_rx_sof signal toggles once the link training block has achieved frame synchronization. The Stat_lt_rx_sof signal continues to toggle High for one clock duration at the training frame boundary.
  5. When link training completes stat_lt_signal_detect asserts and indicates the start of normal PCS operation
  6. An_autoneg_complete goes High when block lock, synchronization, and alignment (if multi-lane core), stat_rx_status and stat_rx_valid_ctrl_code (stat_rx_valid_ctrl_code is only applicable to single lane 10G/25G core) go High.
  7. An_autoneg_complete must go High within the 500 ms timeout or AN will restart. If stat_rx_status goes Low at any time, AN restarts.