The rsfec_bypass_tx_din_cw_start signal must be
asserted to indicate the start of a new RS codeword. If the start signal is
reasserted at any time, the core re-synchronizes to the latest start. On the cycle
when rsfec_bypass_tx_din_cw_start is high, the first 330 bits of
codeword data are transferred into the core, where bit 0 (LSB) is the first bit of
the codeword. The data transfer continues in this way for a total of 16 cycles. On
the 16th cycle, the most significant 140 bits should be padded with zeroes, as these
are the positions of the parity bits that will be added by the encoder. On the 17th
cycle the encoder is ready to accept another pulse on
rsfec_bypass_tx_din_cw_start and begin processing the next
codeword.
The rsfec_bypass_tx_dout_cw_start signal is asserted
at the start of the RS codeword on the output. The
rsfec_bypass_tx_dout_valid signal is asserted when the
corresponding TX data is present on the output. The data output format follows the
data input, with the zero padding replaced by 140 parity bits.