TX debugging is assisted using several diagnostic signals. See Table 1 for more details.
Data must be written to the TX LBUS so that there are no overflow or underflow conditions.
The LBUS bandwidth must always be greater than the Ethernet bandwidth to guarantee that data can be sent without interruption.
When writing data to the LBUS, the tx_rdyout signal must always be observed.
This signal indicates whether the fill level of the TX buffer is within an
acceptable range or not. If this signal is deasserted, you must stop writing
to the TX LBUS until the signal is asserted. Because the TX LBUS has greater
bandwidth than the TX Ethernet interface, it is not unusual to see this
signal being frequently asserted and this is not a cause for concern.
The level at which tx_rdyout becomes asserted is set by a
pre-determined threshold.
tx_rdyout is ignored, the signal tx_ovfout might be asserted, indicating a buffer overflow.
This should be prevented. AMD recommends that
the core be reset if tx_ovfout is asserted.
Do not attempt to continue debugging after tx_ovfout has been asserted until the cause of the
overflow has been addressed. When a packet data transaction has begun in the
TX direction, it must continue until completion or there might be a buffer
underflow as indicated by the signal stat_tx_underflow_err. This must not be allowed to occur. Data
must be written on the TX LBUS without interruption. Ethernet packets must
be present on the line from start to end with no gaps or idles. If stat_tx_underflow_err is asserted, debugging
must stop until the condition which caused the underflow has been
addressed.