General Tab - 3.1 English

UltraScale+ Devices Integrated 100G Ethernet Subsystem LogiCORE IP Product Guide (PG203)
Document ID
PG203
Release Date
2024-07-17
Version
3.1 English

The General Configuration tab configures the Integrated 100G Ethernet core features. See the following figure.

Figure 1. General Tab

The following table describes the General tab options.

Table 1. General Tab
Parameter Description Default Value Range
Physical Layer
Mode 100G Ethernet Mode CAUI 10

CAUI 10

CAUI 4

100GAUI 2

100GAUI 4

Runtime Switchable
Line Rate Number of lanes and line rate 10 lanes x 10.3125 Gb/s

10 lanes x 10.3125 Gb/s

4 lanes x 25.7812 Gb/s

2 lanes x 53.125 Gb/s

4 lanes x 26.5625 Gb/s
Transceiver Type 1 Transceiver Type GTY

GTH

GTY

GTM
GT RefClk Reference clock for the GTs used 156.25 MHz

103.12 MHz

128.90 MHz

156.25 MHz

161.13 MHz

195.31 MHz

201.41 MHz

206.25 MHz

257.81 MHz

309.37 MHz

312.50 MHz

322.266 MHz
Operation Operating mode Duplex

Simplex TX

Simplex RX

Duplex
Clocking Clocking mode Asynchronous Asynchronous
User Interface User Interface LBUS

LBUS

AXIS
GT DRP/Init Clock This specifies the frequency (in MHz) that is used to provide a free running clock to GT and also for the DRP operations 100.00 50 to 250 MHz
Enable TX OTN Interface Selecting this option will include TX Optical Transport Network (OTN) RTL Interface.
  • This feature is available in CAUI-10 and CAUI-4 mode.
 0

0: Disabled

1: Enabled
Link Layer – Transmit
TX Frame CRC 2 TX Frame CRC checking Enable FCS insertion

Enable FCS Insertion

Disable FCS Insertion
Enable TX Lane0 VLM BIP7 Override Port 2 TX Lane0 VLM BIP7 Override 0

0: Disabled

1: Enabled
Link Layer – Receive
RX Frame CRC 3 RX Frame CRC checking Enable FCS stripping

Enable FCS stripping

Disable FCS stripping
Max Pkt Len 3 Maximum Packet Length 9,600 64 to 16383
Min Pkt Len 3 Minimum Packet Length 64 64 to 255
Check Preamble 3 Check Preamble 0

0: Disabled

1: Enabled
Check SFD 3 Check SFD 0

0: Disabled

1: Enabled
Process LFI 3

RX Process LFI

(Local Fault Indication)

 0

0: Disabled

1: Enabled
Link Layer – Flow Control
Enable Transmit Flow Control Enable Transmit Flow Control 1

0: Disabled

1: Enabled
Enable Receive Flow Control Enable Receive Flow Control 1

0: Disabled

1: Enabled
Enable RX Forward Control Frames 4 Forward Control Frames 0

0: Disabled

1: Enabled
Enable Receive Check ACK Enable Receive Check ACK 1

0: Disabled

1: Enabled
Link Layer – IEEE PTP 1588v2
Enable Time Stamping Enables timestamping 0

0: Disabled

1: Enabled
Operation Mode

Select the Operation Mode.

Unavailable when Enable Time Stamping = 0

 Two Step

One Step

Two Step

Both
Clocking Mode

Select the Clocking Mode.

Unavailable when Enable Time Stamping = 0

 Ordinary Clock

Ordinary Clock

Transparent Clock
TX Latency Adjust 1-step with 2-step

Unavailable when Enable

Time Stamping = 0 with default value as 0.

Only available when Operation Mode is Both .

If the clocking mode is ordinary clock, default value is 705.

If clocking mode is transparent clock, default value should be 802.

 0 0 to 2,047
Enable VLane Adjust Mode

Unavailable when Enable Time Stamping = 0.

Available when operation mode is One Step or Both .

 0

0: Disabled

1: Enabled
Link Layer – TX Interpacket Gap
TX IPG Value TX Interpacket Gap Value 12 8 to 12 (integer)
Additional Features
Include IEEE 802.3bj RS-FEC 5 Selecting this option will include IEEE 802.3bj RS-FEC in between CMAC and GT.

For 100GAUI-2 mode, the KP4 FEC Transcode within the GTM is enabled and grayed out.

  • This feature is available in 100GAUI-2, CAUI-4, and Runtime Switchable mode.
 0

0: Disabled

1: Enabled
Include AN/LT Logic

Selecting this option will include AN/LT soft logic.

  • This feature is available in CAUI-4 mode only.
 0

0: Disabled

1: Enabled
Include AXI4-Lite Control and Statistics Interface When you enable, the AXI4-Lite interface is provided in the core. 0

0: Disabled

1: Enabled
Include Statistics Counters

Selecting this option will include the statistics counters in the AXI4-Lite registers.

  • This feature is enabled when Include AXI4-Lite Control and Statistics Interface is selected.
 0

0: Disabled

1: Enabled
Statistics Resource Type

This option indicates the type of implementation of the statistics counters.

  • This feature is enabled when Include AXI4-Lite Control and Statistics Interface and Include Statistics Counters are selected.
 Registers

Registers

Block RAM 6

  1. Transceivers are selected as per the availability based on the devices.
  2. Requires TX to be enabled. Operation = Simplex TX or Duplex modes only.
  3. Requires RX to be enabled. Operation = Simplex RX or Duplex modes only.
  4. Option is disabled when receive flow control is disabled.
  5. For 100GAUI-2 mode, it is “Include KP4 FEC Transcode” configuration. In this case, the KP4 FEC Transcode within the GTM is used.
  6. Block RAM usage for the Statistics counters will be supported in a future release.