PCS - 3.1 English

UltraScale+ Devices Integrated 100G Ethernet Subsystem Product Guide (PG203)

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3.1 English

This section refers to the PCS lane logic within the CMAC block and not the PCS within the serial transceiver. The PCS lane logic architecture is based on distributing (or striping) parts of a packet over several (relatively) lower speed physical interfaces by the transmitting device.

The receiving device PCS lane logic is then responsible for de-striping the different parts and rebuilding the packet before handing it off to the CMAC block.

The receiver PCS lane logic must also deskew the data from the different physical interfaces as these might see different delays as they are transported throughout the network. Additionally, the core handles PCS lane swapping across all received PCS lanes, allowing the 100G Ethernet IP core to be used with all optical transport systems.

The PCS lane logic includes scrambling/descrambling and 64B/66B encoders/decoders capable of supporting the 100 Gb/s line rate. The frequency at which the PCS runs at is shown in Table: 100G PCS Frequencies.

Table 3-2:      100G PCS Frequencies


GT Interface Width

100G PCS Frequency (MHz)

100G (2 x 53.125)



100G (4 x 26.5625)/

100G (4 x 25.78125)

with GTY: 80

with GTM: 64(1)


100G (10 x 10.3125)




1.The 100GAUI-4/CAUI-4 mode with GTM configuration is with GTM_NRZ type configuration.