Product Specification - 3.1 English - PG203

UltraScale+ Devices Integrated 100G Ethernet Subsystem LogiCORE IP Product Guide (PG203)

Document ID
PG203
Release Date
2024-07-17
Version
3.1 English

The following table defines the integrated CMAC block for the 100 Gb/s Ethernet solution.

Table 1. Integrated CMAC Block for the 100 Gb/s Ethernet Solution
Protocol Lane Width Line Rate SerDes SerDes Width
CAUI-10 x10 10.3125 Gb/s

GTH

GTY

32b
CAUI-4 x4 25.78125 Gb/s 2 GTY 1

GTM

With GTY: 80b

With GTM: 64b

Runtime Switchable CAUI-4/CAUI-10

CAUI-10: x10

CAUI-4: x4

CAUI-10: 10.3125 Gb/s

CAUI-4: 25.78125 Gb/s

GTY 1

CAUI-10: 32b

CAUI-4: 80b

100GAUI-2 x2 53.125 Gb/s 3 GTM 160b
100GAUI-4 x4 26.5625 Gb/s

GTY 4

GTM

With GTY: 80b

With GTM: 64b

  1. CAUI-4 requires GTY or GTM transceivers which are available in select devices. Runtime switchable CAU-10/CAUI-4 require GTY transceivers available only in select devices.
  2. The line rate of 25.78125 Gb/s is available on select devices in typical speed grades.
  3. The line rate of 53.125 Gb/s (GTM transceivers) is available on select devices.
  4. 100GAUI-4 requires GTY or GTM transceivers which are available in select devices.

The core instantiates the CMAC block along with the necessary GTH, GTY, or GTM transceivers. The core provides an example of how the two blocks are connected together, along with the reset and clocking for those blocks.

The integrated block is designed to IEEE std 802.3-2012.

The following figure illustrates the following interfaces to the integrated CMAC block.

  • Serial transceiver interface
  • User-side transmit and receive LBUS or AXIS interface
  • Pause processing
  • IEEE 1588-2008 timestamping interface
  • Status/Control interface
  • DRP interface used for configuration
  • RS-FEC IP Block
Figure 1. Integrated CMAC Block for 100 Gb/s Ethernet
Page-1 Sheet.1 Sheet.2 Sheet.3 TX and RX TX and RX Sheet.4 PCS PCS Sheet.5 Sheet.6 RX MAC RX MAC Sheet.7 Sheet.8 TX MAC TX MAC Sheet.9 RX LBUS Interface RX LBUSInterface Sheet.10 Sheet.11 Status/Control Status/Control Sheet.12 Status/ Status/ Sheet.13 Control Control Sheet.14 Sheet.15 RS-FEC IP Block (for CAUI-4 only) RS-FEC IP Block (for CAUI-4 only) Sheet.16 LBUS LBUS Sheet.17 LBUS LBUS Sheet.18 PAUSE PROCESSING PAUSE PROCESSING Dynamic connector Dynamic connector.70 Dynamic connector.71 Dynamic connector.82 Dynamic connector.89 Dynamic connector.74 Sheet.25 TX LBUS Interface TX LBUSInterface Dynamic connector.77 Sheet.27 Configuration Configuration Sheet.28 DRP DRP Dynamic connector.80 Dynamic connector.81 Sheet.31 DRP Interface DRP Interface Sheet.32 IEEE 1588 IEEE 1588 Dynamic connector.92 Sheet.34 IEEE 1588 Timestamping Interface IEEE 1588 Timestamping Interface Sheet.35 GTH/GTY/GTM GTH/GTY/GTM Sheet.36 GTH/GTY/GTM GTH/GTY/GTM Dynamic connector.9 Sheet.38 GTH/GTY/GTM GTH/GTY/GTM Sheet.39 GTH/GTY/GTM GTH/GTY/GTM Sheet.40 GTH/GTY GTH/GTY Sheet.41 GTH/GTY GTH/GTY Sheet.42 GTH/GTY GTH/GTY Sheet.43 GTH/GTY GTH/GTY Sheet.44 GTH/GTY GTH/GTY Sheet.45 GTH/GTY GTH/GTY Sheet.46 Transceiver Interface Transceiver Interface Dynamic connector.7 Dynamic connector.11 Dynamic connector.13 Dynamic connector.15 Dynamic connector.17 Dynamic connector.19 Dynamic connector.21 Dynamic connector.23 Dynamic connector.25 Dynamic connector.3 Dynamic connector.5 Dynamic connector.31 Sheet.60 Transcode Bypass Mode Transcode BypassMode Dynamic connector.33 Dynamic connector.34 Sheet.63 Transcode Bypass Interface Transcode Bypass Interface Sheet.64 CMAC CMAC Sheet.65 TX and RX RS-FEC TX and RX RS-FEC Dynamic connector.29 Sheet.67 Pause Processing Pause Processing Sheet.68 X17785-102918 X17785-102918