The 100G Ethernet IP core provides
status signals to identify 64B/66B words and sequences violations and CRC32 checking
failures. All signals are synchronous with the rising-edge of CLK. A detailed description of each signal
follows.
STAT_RX_BAD_FCS[2:0]
When this signal is a value of 1, it indicates that the error detection logic has identified a mismatch between the expected and received value of CRC32 in the received packet.
When a CRC32 error is detected, the
received packet is marked as containing an error and it is sent with RX_ERROUT asserted during the last transfer (the cycle
with RX_EOPOUT asserted), unless CTL_RX_IGNORE_FCS is asserted. This signal is asserted
for one clock period each time a CRC32 error is detected.
STAT_RX_BAD_CODE[2:0]
This signal indicates how many cycles the RX PCS receive state machine is in the RX_E state as defined by the 802.3-2012 specifications.