AXI User Interface Ports - 3.1 English

UltraScale+ Devices Integrated 100G Ethernet Subsystem LogiCORE IP Product Guide (PG203)

Document ID
PG203
Release Date
2024-07-17
Version
3.1 English

AXI User Interface Ports

The AXI user interface ports are listed in the following table.

Table 1. AXI User Interface Ports
Name Size I/O Description
s_axi_aclk 1 I AXI clock signal
s_axi_sreset 1 I AXI active-High synchronous reset
s_axi_awaddr 32 I AXI write address
s_axi_awvalid 1 I AXI write address valid
s_axi_awready 1 O AXI write address ready
s_axi_wdata 32 I AXI write data
s_axi_wstrb 4 I AXI write strobe. This signal indicates which byte lanes hold valid data.
s_axi_wvalid 1 I AXI write data valid. This signal indicates that valid write data and strobes are available.
s_axi_wready 1 O AXI write data ready
s_axi_bresp 2 O

AXI write response. This signal indicates the status of the write transaction.

  • ‘b00 = OKAY
  • ‘b01 = EXOKAY
  • ‘b10 = SLVERR
  • ‘b11 = DECERR
s_axi_bvalid 1 O AXI write response valid. This signal indicates that the channel is signaling a valid write response.
s_axi_bready 1 I AXI write response ready.
s_axi_araddr 32 I AXI read address
s_axi_arvalid 1 I AXI read address valid
s_axi_arready 1 O AXI read address ready
s_axi_rdata 32 O AXI read data issued by slave
s_axi_rresp 2 O

AXI read response. This signal indicates the status of the read transfer.

  • ‘b00 = OKAY
  • ‘b01 = EXOKAY
  • ‘b10 = SLVERR
  • ‘b11 = DECERR
s_axi_rvalid 1 O AXI read data valid
s_axi_rready 1 I AXI read ready. This signal indicates the user/master can accept the read data and response information.