Signal Integrity - 3.1 English

UltraScale+ Devices Integrated 100G Ethernet Subsystem Product Guide (PG203)

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3.1 English

If you are bringing up a board for the first time and the 100G Ethernet IP core does not seem to be achieving lane alignment, the most likely problem is related to signal integrity. Signal integrity issues must be addressed before any other debugging can take place.

Even if lane alignment is achieved, periodic BIP8 errors create signal integrity issues. Check the BIP8 signals to assist with debugging.


IMPORTANT:   It assumed that the PCB itself has been designed and manufactured in accordance with the required trace impedances and trace lengths, including the requirements for skew set out in the IEEE 802.3 specification.)

Signal integrity should be debugged independently from the 100G Ethernet IP core. The following checks should be made:

Transceiver Settings

Checking For Noise

Bit Error Rate Testing

If assistance is required for transceiver and signal integrity debugging, contact technical support.