UltraScale+ Device RS-FEC for Integrated 100G Ethernet - 3.1 English - PG203

UltraScale+ Devices Integrated 100G Ethernet Subsystem LogiCORE IP Product Guide (PG203)

Document ID
PG203
Release Date
2024-07-17
Version
3.1 English

Reed-Solomon Forward Error Correction (RS-FEC) provides a robust multi-bit error detection and correction algorithm that protects the full 100 Gigabit data stream. This appendix describes the integration of the RS-FEC engine within the AMD UltraScale+ device integrated 100G Ethernet IP. For a detailed description of the RS-FEC sublayer, refer to IEEE 802.3bj-2014 Clause 91 .

Figure 1. Block Diagram of 100G Ethernet MAC With RS-FEC Block (CMAC) Page-1 Process.507 GTY/GTH Quad 10G GTY/GTH Quad 10G Process.3 GTY Quad 25G GTY Quad 25G Process.4 GTY/GTH Quad 10G GTY/GTH Quad 10G Process.5 RS-FEC IP Block RS-FEC IP Block Text Arrow.530 4x32b 4x32b Text Arrow.12 4x80/32b 4x80/32b Text Arrow.13 2x32b 2x32b Text Arrow.14 4x32b 4x32b Process.15 Text Arrow.16 4x80/32b 4x80/32b Text Arrow.17 2x32b 2x32b Sheet.18 Sheet.19 100GbE PCS 100GbE PCS Sheet.21 100GbE MAC 100GbE MAC Sheet.22 X17808-022317 X17808-022317