The 100G Ethernet IP core provides
status bits to indicate the state of word boundary synchronization and PCS lane
alignment. All signals are synchronous with the rising-edge of RX _CLK. A detailed description of each signal
follows.
STAT_RX_SYNCED[19:0]
When a bit of this bus is 0, it indicates that word boundary synchronization of the corresponding lane is not complete or that an error has occurred as identified by another status bit.
When a bit of this bus is 1, it indicates that the corresponding lane is word boundary synchronized and is receiving PCS Lane Marker Words as expected.
STAT_RX_SYNCED_ERR[19:0]
When a bit of this bus is 1, it indicates one of several possible failures on the corresponding lane.
- Word boundary synchronization in the lane was not possible using Framing bits [65:64].
- After word boundary synchronization in the lane was achieved, errors were detected on Framing bits [65:64].
- After word boundary synchronization in the lane was achieved, a valid PCS Lane Marker Word was never received.
The bits of the bus remain asserted until word boundary synchronization occurs or until some other error/failure is signaled for the corresponding lane.
STAT_RX_MF_LEN_ERR[19:0]
When a bit of this bus is 1, it indicates that PCS Lane Marker Words are being received but not at the expected rate in the corresponding lane. The transmitter and receiver must be re-configured with the same Meta Frame length.
The bits of the bus remain asserted until word boundary synchronization occurs or until some other error/failure is signaled for the corresponding lane.
STAT_RX_MF_REPEAT_ERR[19:0]
After word boundary synchronization is achieved in a lane, if a bit of this bus is a 1, it indicates that four consecutive invalid PCS Lane Marker Words were detected in the corresponding lane.
The bits of the bus remain asserted until re- synchronization occurs or until some other error/failure is signaled for the corresponding lane.
STAT_RX_MF_ERR[19:0]
When a bit of this bus is 1, it indicates that an invalid PCS Lane Marker Word was received on the corresponding lane. This bit is only asserted after word boundary synchronization is achieved. This output is asserted for one clock period each time an invalid Meta Packet Synchronization Word is detected.
STAT_RX_ALIGNED
When STAT_RX_ALIGNED is a value of 1, all of the lanes are
aligned/de-skewed and the receiver is ready to receive packet data.
STAT_RX_ALIGNED_ERR
When STAT_RX_ALIGNED_ERR is a value of 1, one of two things occurred. Lane
alignment failed after several attempts, or lane alignment was lost (STAT_RX_ALIGNED was asserted and then it was
negated).
STAT_RX_MISALIGNED
When STAT_RX_MISALIGNED is a value of 1, a valid PCS Lane Marker Word was
not received on all PCS lanes simultaneously. This output is asserted for one clock
period each time this error condition is detected.
STAT_RX_FRAMING_ERR_[0-19][1:0] and STAT_RX_FRAMING_ERR_VALID_[0-19]
This set of buses is intended to be used
to keep track of sync header errors. There is a pair of outputs for each PCS Lane.
The STAT_RX_FRAMING_ERR_[0-19] output bus
indicates how many sync header errors were received and it is qualified (that is,
the value is only valid) when the corresponding STAT_RX_FRAMING_ERR_VALID[0-19] is sampled as a 1.
STAT_RX_PCSL_NUMBER_[0-19][4:0]
Each bus indicates which PCS lane will
have its status reflected on a specific status pins. For example, STAT_RX_PCSL_NUMBER_0 indicates which PCS lane will
have its status reflected on pin 0 of the other status signals. These buses can be
used to detect if a PCS lane has not been found or if one has been mapped to
multiple status pins.
In CAUI-10 mode:
- The physical lanes 0, 1 map to GT0,
- The physical lanes 2, 3 map to GT1,
- The physical lanes 4, 5 corresponds to GT2, and so forth.
In CAUI-4 mode:
- The physical lanes 0, 1, 2, 3, 4 map to GT0,
- The physical lanes 5, 6, 7, 8, 9 map to GT1,
- The physical lanes 10, 11, 12, 13, 14 map to GT2, and
- The physical lanes 15, 16, 17, 18, 19 map to GT3.
STAT_RX_PCSL_DEMUXED[19:0]
After word boundary synchronization is achieved on each lane, if a bit of this bus is 1 it indicates that the corresponding PCS lane was properly found and demultiplexed.
STAT_RX_BLOCK_LOCK[19:0]
Each bit indicates that the corresponding PCS lane has achieved sync header lock as defined by the 802.3-2012. A value of 1 indicates block lock is achieved.
STAT_RX_STATUS
This output is set to a 1 when STAT_RX_ALIGNED is a 1 and STAT_RX_HI_BER is a 0. This is defined by the 802.3-2012.
STAT_RX_LOCAL_FAULT
This output is High when STAT_RX_INTERNAL_LOCAL_FAULT or STAT_RX_RECEIVED_LOCAL_FAULT is asserted. This output
is level sensitive.