Without AXI4-Lite Interface - 3.1 English

UltraScale+ Devices Integrated 100G Ethernet Subsystem Product Guide (PG203)

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3.1 English

1.Assert the below signals:

ctl_rx_enable = 1’b1

ctl_tx_send_rfi = 1’b1

2.Wait for RX_aligned then deassert / assert the below signals:

ctl_tx_send_rfi = 1’b0

ctl_tx_enable = 1’b1

3.When TX/RX flow control is enabled in the Vivado IDE (the default setting), assign the below signals.

Note:   If you have disabled TX/RX flow control in the Vivado IDE, skip to step 4.

ctl_tx_pause_req[8:0] = 9’b100

ctl_rx_pause_enable[8:0] = 9’b1FF

ctl_tx_pause_enable[8:0] = 9’b1FF

ctl_tx_pause_quanta8[15:0] = 16’bFFFF

ctl_tx_pause_refresh_timer8[15:0] = 16’bFFFF

4.Data transmission and reception can be performed.