UltraScale to UltraScale+ FPGA Enhancements - 3.1 English

UltraScale+ Devices Integrated 100G Ethernet Subsystem LogiCORE IP Product Guide (PG203)

Document ID
PG203
Release Date
2024-07-17
Version
3.1 English

The AMD UltraScale+ Integrated 100G Ethernet IP is derived from UltraScale Integrated 100G Ethernet IP (described in UltraScale Devices Integrated 100G Ethernet LogiCORE IP Product Guide (PG165)) with a few enhancements and minor modifications, as documented in this appendix.