General Checks - 3.1 English

UltraScale+ Devices Integrated 100G Ethernet Subsystem Product Guide (PG203)

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3.1 English

Ensure that all the timing constraints for the core are properly incorporated from the example design and that all constraints are met during implementation.

Does it work in post-place and route timing simulation? If problems are seen in hardware but not in timing simulation, this could indicate a PCB issue. Ensure that all clock sources are active and clean.

If using MMCMs in the design, ensure that all MMCMs have obtained lock by monitoring the locked port.