RS-FEC Enabled Configuration Simulation - 3.1 English

UltraScale+ Devices Integrated 100G Ethernet Subsystem LogiCORE IP Product Guide (PG203)

Document ID
PG203
Release Date
2024-07-17
Version
3.1 English

For faster simulation, apply SIM_SPEED_UP and disable the Use Precompiled IP Simulation Libraries check box in the simulation setting window as in the following figure. Otherwise, simulation will run for a very long time and will timeout with error.

Figure 1. SIM_SPEED_UP Enabled

Figure 2. Use Precompiled IP Simulation Libraries Disabled