The integrated CMAC block has a total of 12 resets. They are
TX_RESET, RX_RESET, and
RX_SERDES_RESET[9:0]. During configuration TX_RESET,
RX_RESET, and RX_SERDES_RESET[9:0] need to be asserted
High and after the clocks are stable, the resets are released. During normal operation the RX
and TX paths can be asserted independently. Within the RX and TX logic paths, there are
separate resets to the core and the lane logic. The reset procedure is simple and the only
requirement is that a reset must be asserted until the corresponding clock(s) are stable. The
100G Ethernet IP core takes care of ensuring that the different resets are properly
synchronized to the required domain. It is up to you to ensure a reset is held until the
corresponding clock is fully stable.
The 100G Ethernet IP core provides sys_reset input to reset
GTs and integrated CMAC block and gtwiz_reset_tx_datapath and
gtwiz_reset_rx_datapath to reset GT and CMAC RX and TX datapaths
individually.
RX_RESET or
TX_RESET ) must be asserted until the control input is stabilized. All
resets within the block are asynchronously asserted, and synchronously deasserted. Standard
cell synchronizers are used, where applicable per guidelines to synchronize assertion and
release of resets to respective clock inputs.See the following figures for diagrams of the clocking and resets. The
available modes are based on the AMD Vivado™
Integrated Design
Environment (IDE) selection and configuration. For Asynchronous mode,
TXOUTCLK sources the TXUSRCLK, and
RXOUTCLK sources the RXUSRCLK. Asynchronous Mode allows
per specification PPM difference between clocks.
