Worst Case Power Analysis Using Xilinx Power Estimator (XPE) - 2020.2 English

UltraFast Design Methodology Guide for Xilinx FPGAs and SoCs

Document ID
UG949
Release Date
2021-02-18
Version
2020.2 English

Xilinx recommends designing the board for worst-case power. For details, see this link in the Vivado Design Suite User Guide: Power Analysis and Optimization (UG907).