Incremental Synthesis - 2020.2 English

UltraFast Design Methodology Guide for Xilinx FPGAs and SoCs

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2020.2 English

You can use incremental synthesis to reuse existing synthesis results. This approach offers the following advantages:

  • Reduces typical synthesis compile times by 50%.
  • When used with the incremental implementation flow, improves overall compile time and timing closure consistency.

Incremental synthesis has the highest value when the top-level design is RTL and RTL makes up a significant portion of the design. In this mode, synthesis compile time is optimized and results are reused. For designs that include a significant amount of block designs, IP, or both, the Vivado tools automatically separate synthesis on these blocks and run synthesis in out-of-context (OOC) mode. As a result, incremental synthesis has less value on these designs.

For designs that are mostly RTL that use OOC synthesis flows to reduce run time or variations between runs, it might be advantageous to convert the OOC runs to an incremental synthesis flow. The incremental synthesis flow helps maintain a faster run time with less variations in runs but allows for more opportunities for synthesis to optimize for QoR. When converting to an incremental synthesis flow, you must move timing constraints from the OOC run to the top level.

You can enable incremental synthesis with no negative impact on QoR. The post-synthesis design checkpoint approximately doubles in size, and there is a negligible increase in compile time when synthesis data is read but not reused.

Incremental synthesis reduces compile time by reusing unmodified hierarchies from the reference synthesis run. For incremental synthesis to be effective, the design must contain at least 5 partitions of at least 10000 instances. In addition, any design changes must impact as few partitions as possible and must not be at the top level of the design.

Note: Some changes might impact cross-boundary optimization, which results in additional partitions requiring resynthesis.

If you know which hierarchy will be modified, you can use the following property to preserve the hierarchy. This allows incremental synthesis to reoptimize only the preserved hierarchy in future synthesis runs. However, this property prevents cross-boundary optimizations, which might have an impact on QoR.

set_property BLOCK_SYNTH.PRESERVE_BOUNDARY [get_cells <cellName>]
Important: If you change synthesis settings from the reference run, the Vivado tools automatically default to a full resynthesis.

For more information, see the Vivado Design Suite User Guide: Synthesis (UG901).