Fixing Issues Flagged by report_methodology - 2020.2 English

UltraFast Design Methodology Guide for Xilinx FPGAs and SoCs

Document ID
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2020.2 English

The report_methodology command reports additional constraints and timing analysis issues, which you must carefully review before and after running the place and route tools. This section describes the main XDC and TIMING categories of checks, along with their relative impact on timing closure and hardware stability. You must focus on resolving the checks that impact timing closure first.

See Timing Methodology Checks in Vivado Design Suite User Guide: Design Analysis and Closure Techniques (UG906) for more information on some of the following checks.