BUFG_GT Divider - 2020.2 English

UltraFast Design Methodology Guide for Xilinx FPGAs and SoCs

Document ID
Release Date
2020.2 English

The BUFG_GT buffers can drive any loads in the fabric and include an optional divider you can use to divide the clock from the GT*_CHANNEL. This eliminates the need to use an extra MMCM or BUFG_DIV to divide the clock.