Clock Enables - 2020.2 English

UltraFast Design Methodology Guide for Xilinx FPGAs and SoCs

Document ID
Release Date
2020.2 English

When used properly, clock enables can significantly reduce design power with little impact on area or performance. However, when clock enables are used improperly, they can lead to:

  • Increased resource utilization
  • Decreased placement density
  • Increased power
  • Reduced performance

In most cases, low fanout clock enables are the main contributor to the high number of control sets.