Auto-Derived Clocks - 2020.2 English

UltraFast Design Methodology Guide for Xilinx FPGAs and SoCs

Document ID
Release Date
2020.2 English

Most generated clocks are automatically derived by the Vivado timing engine which recognizes the clock modifying blocks (CMB) and the transformation they perform on the master clocks.

In the Xilinx 7 series device family, the CMBs are:

  • MMCM*/ PLL*
  • BUFR

In the Xilinx UltraScale device family, following are the CMBs:

  • MMCM* / PLL*

For any other combinatorial cell located on the clock tree, the timing clocks propagate through them and do not need to be redefined at their output, unless the waveform is transformed by the cell. In general, you must rely on the auto-derivation mechanism as much as possible as it provides the safest way to define the generated clocks that correspond to the actual hardware behavior.

If the auto-derived clock name chosen by the Vivado Design Suite timing engine does not seem appropriate, you can force your own name by using the create_generated_clock command without specifying the waveform transformation. This constraint should be located right after the constraint that defines the master clock in the constraint file. For example, if the default name of a clock generated by a MMCM instance is net0, you can add the following constraint to force your own name (fftClk in the given example):
create_generated_clock -name fftClk [get_pins mmcm_i/CLKOUT0]

To avoid any ambiguity, the constraint must be attached to the source pin of the clock. For more information, see Vivado Design Suite User Guide: Using Constraints (UG903).