Using the CLOCK_DEDICATED_ROUTE Constraint - 2020.2 English

UltraFast Design Methodology Guide for Xilinx FPGAs and SoCs

Document ID
UG949
Release Date
2021-02-18
Version
2020.2 English

The CLOCK_DEDICATED_ROUTE constraint is typically used when driving from a clock buffer in one clock region to an MMCM or PLL in another clock region. By default, the CLOCK_DEDICATED_ROUTE constraint is set to TRUE, and the buffer/MMCM or PLL pair must be placed in the same clock region.

Note: Using the 7 series CLOCK_DEDICATED_ROUTE value of BACKBONE on an UltraScale device results in the same behavior as SAME_CMT_COLUMN.

The following table summarizes the different CLOCK_DEDICATED_ROUTE constraint values, use, and behavior.

Table 1. UltraScale Device CLOCK_DEDICATED_ROUTE Constraint Summary
Value Use Behavior
TRUE Default value on clock nets

Global clock buffer and MMCM/PLLs must be placed in the same clock region.

This value ensures the net is routed using only global clock resources.

SAME_CMT_COLUMN

(BACKBONE)

Net driven by a global clock buffer

Example:

set_property CLOCK_DEDICATED_ROUTE SAME_CMT_COLUMN \
[get_nets -of [get_pins BUFGCE_inst/O]]

MMCM/PLLs must be placed in a clock region in the same vertical column.

This value ensures the net is routed using only global clock resources.

For optimal results, Xilinx recommends using a LOC constraint on the MMCM/PLL to control placement of the MMCM/PLL within in the same vertical column.

ANY_CMT_COLUMN

Net driven by a global clock buffer

Examples:

set_property CLOCK_DEDICATED_ROUTE ANY_CMT_COLUMN \
[get_nets -of [get_pins BUFGCE_inst/O]]
set_property CLOCK_DEDICATED_ROUTE ANY_CMT_COLUMN \
[get_nets -of [get_pins BUFGCE_DIV_inst/O]]
set_property CLOCK_DEDICATED_ROUTE ANY_CMT_COLUMN \
[get_nets -of [get_pins BUFGCTRL_inst/O]]

MMCM/PLLs can be placed in any clock region with available resources.

This value ensures the net is routed using only global clock resources.

For optimal results, Xilinx recommends using a LOC constraint on the MMCM/PLL to control placement of the MMCM/PLL within the device.

FALSE

Clock net not driven by a global clock buffer but part of the clock network (for example, nets driven by the output of an IBUF or nets directly connected to output clock pins of an MMCM)

Examples:

set_property CLOCK_DEDICATED_ROUTE FALSE \
[get_nets -of [get_pins MMCME4_ADV_inst/CLKOUT0]]
set_property CLOCK_DEDICATED_ROUTE FALSE \
[get_nets -of [get_pins IBUF_inst/O]]

Net is routed using fabric and global clock resources.

This can adversely affect the timing and performance of the clock network.

Important: For UltraScale devices, the FALSE value must only be used when a clock normally routed with global clock resources needs to be routed with fabric resources for special design reasons.
Note: When working with UltraScale devices, do not apply the CLOCK_DEDICATED_ROUTE property to the net driven directly by a port. Instead, apply the CLOCK_DEDICATED_ROUTE property to the output of the IBUF.

Constraint Example for Vertically Adjacent Clock Regions

When driving from a clock buffer in one clock region to a MMCM or PLL in a vertically adjacent clock region, you must set the CLOCK_DEDICATED_ROUTE to BACKBONE for 7 series devices or to SAME_CMT_COLUMN for UltraScale devices. This prevents implementation errors and ensures that the clock is routed with global clock resources only. The following example and figure show a clock buffer driving two PLLs in vertically adjacent clock regions.

set_property CLOCK_DEDICATED_ROUTE SAME_CMT_COLUMN [get_nets -of [get_pins BUFG_inst_0/O]]
set_property LOC PLLE3_ADV_X0Y0 [get_cells PLLE3_ADV_inst_0]
set_property LOC PLLE3_ADV_X0Y4 [get_cells PLLE3_ADV_inst_1]
Figure 1. CLOCK_DEDICATED_ROUTE Constraint Set to SAME_CMT_COLUMN

Constraint Example for Non-Vertically Adjacent Clock Regions

When driving from a clock buffer to other clock regions that are not vertically adjacent, you must set the CLOCK_DEDICATED_ROUTE to FALSE for 7 series devices or to ANY_CMT_COLUMN for UltraScale devices. This prevents implementation errors and ensures that the clock is routed with global clock resources only. The following example and figure show a BUFGCE driving two PLLs that are not located on the same clock region column as the input buffer.

set_property CLOCK_DEDICATED_ROUTE ANY_CMT_COLUMN [get_nets -of [get_pins BUFG_inst_0/O]]
set_property LOC PLLE3_ADV_X1Y0 [get_cells PLLE3_ADV_inst_0]
set_property LOC PLLE3_ADV_X1Y4 [get_cells PLLE3_ADV_inst_1]
Figure 2. CLOCK_DEDICATED_ROUTE Set to ANY_CMT_COLUMN