Post-Synthesis and Post-Logic Optimization - 2020.2 English

UltraFast Design Methodology Guide for Xilinx FPGAs and SoCs

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2020.2 English

Estimated net delays are close to the best possible placement for all paths. To fix violating paths try the following:

  • Change the RTL.
  • Use different synthesis options.
  • Add timing exceptions such as multicycle paths, if appropriate and safe for the functionality in hardware.