Design Closure - 2020.2 English

UltraFast Design Methodology Guide for Xilinx FPGAs and SoCs

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2020.2 English

Design closure consists of meeting all timing, system performance, and power requirements, and successfully validating the functionality in hardware. Design closure usually takes several iterations between results analysis, design modification, and constraints modification. Design closure is often seen as a trade-off between timing and power optimization. However, many optimizations that benefit timing also benefit power. For example, improving placement to shorten distances between cells reduces both propagation delay and interconnect power.

A common mistake is to focus exclusively on timing closure first, then begin power optimization after timing is closed. The majority of power optimizations do not worsen timing but do create variation in the logical netlist. Designs that are on the edge of meeting timing might have trouble maintaining timing closure when power optimization changes are introduced. Xilinx recommends incorporating power optimizations early in the design cycle to avoid iterations between closing timing and closing power.

Tip: See the UltraFast Design Methodology Timing Closure Quick Reference Guide (UG1292) for a condensed version of the techniques described in this chapter, including running initial design checks, baselining the design, and resolving timing violations.