The DRCs shown in the following table do not usually flag issues that impact the ease of closing timing. Instead, these DRCs flag problems with timing analysis accuracy due to non-recommended constraints. Even when setup and hold slacks are positive, the hardware might not function properly under all operating conditions. Most checks refer to clocks not defined on the boundary of the design, clocks with unexpected waveform, missing timing requirements, or inappropriate CDC circuitry. For this last category, use the report_cdc command to perform a more comprehensive analysis.
Important: Carefully verify timing checks with a severity of Critical Warning.
| Check | Severity | Description |
|---|---|---|
| TIMING-1, TIMING-2, TIMING-3, TIMING-4, TIMING-27 | Critical Warning | Non-recommended clock source point definition |
| TIMING-5, TIMING-25, TIMING-19 | Critical Warning | Unexpected clock waveform |
| TIMING-9, TIMING-10 | Warning | Unknown or incomplete CDC circuitry |
| TIMING-11 | Warning | Inappropriate set_max_delay -datapath_only command |
| TIMING-12 | Warning | Clock Reconvergence Pessimism Removal disabled |
| TIMING-13, TIMING-23 | Warning | Incomplete timing analysis due to broken paths |
| TIMING-17 | Critical Warning | Non-clocked sequential cell |
| TIMING-18, TIMING-20, TIMING-26 | Warning | Missing clock or input/output delay constraints |
| TIMING-21, TIMING-22 | Warning | Issues with MMCM compensation |
| TIMING-24 | Warning | Overridden set_max_delay
-datapath_only command |
| TIMING-29 | Warning | Inconsistent pair of multicycle paths |
| TIMING-35 | Critical Warning | No common node in paths with the same clock |
| TIMING-40, TIMING-43 | Warning | Inappropriate clock topologies or requirements |
| TIMING-41 | Warning | Invalid forwarded clock defined on an internal pin |
| TIMING-46 | Warning | Multicycle path with tied CE pins |
| TIMING-47 | Warning | False path or asynchronous clock group between synchronous clocks |
| TIMING-51 | Critical Warning | No common phase between related clocks from parallel MMCMs or PLLs |
| TIMING-52 | Critical Warning | No common phase between related clocks from Spread Spectrum MMCM |